name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv:13:1: error: expected membersyntaxerror^~~~~~~~~~~
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 1(0, 0) source_file(6, 0) module_declaration(12, 0) module_or_generate_item(12, 0) net_declaration(13, 6) ERROR
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv:14: syntax error, unexpected wire, expecting IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv:14: syntax error, unexpected TOK_WIRE, expecting TOK_ID or '#'
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv::14 error in parsing: (syntax error, unexpected netWIRE, expecting vSYMBOL_ID or '#') wire clk;--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: sanity_tb==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.2ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv:13: error: Invalid module instantiation
name: sanitydescription: A simple module that should fail during parsingshould_fail: 1tags: sanityfiles: ['/home/travis/build/SymbiFlow/sv-tests/tests/sanity.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType wire,DTIdent "clk"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: swervdescription: Full swerv core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/configs/snapshots/default/common_defines.vh', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/build.h', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/global.h', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/swerv_types.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_mem_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_div_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_mem.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_wrapper.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_jtag_to_core_sync.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/axi4_to_ahb.sv']incdirs: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/configs/snapshots/default']should_fail: 0tags: swervtop_module: swerv_wrapperrc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/axi4_to_ahb.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/axi4_to_ahb.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (3)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (4)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (5)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (6)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (7)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (8)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (9)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/axi4_to_ahb.sv to parse listAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/ahb_to_axi4.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/mem_lib.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib/beh_lib.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lib//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/rvjtag_tap.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_jtag_to_core_sync.v to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_jtag_to_core_sync.v, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_jtag_to_core_sync.vAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_wrapper.v to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_wrapper.v, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi/dmi_wrapper.vAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dmi//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg/dbg.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dbg//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_trigger.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/desWARNING (10)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_mem.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_mem.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (11)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (12)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (13)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (14)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (15)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (16)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (17)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (18)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (19)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }ign/lsu/lsu_dccm_mem.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_mem.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_dccm_mem.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_ecc.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_intf.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_bus_buffer.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_stbuf.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_lsc_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_addrcheck.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu_clkdomain.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu/lsu.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/lsu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_div_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_div_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/coreWARNING (20)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_div_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_div_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (21)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (22)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (23)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (24)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (25)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (26)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (27)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (28)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (29)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (30)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }s/swerv/design/exu/exu_div_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_mul_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu/exu_alu_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/exu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_trigger.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_tlu_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_ib_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_gpr_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec/dec_decode_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dec//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_iccm_mem.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_mem_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/tWARNING (31)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_mem_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_mem_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (32)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (33)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (34)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (35)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (36)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (37)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (38)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (39)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (40)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (41)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }hird_party/cores/swerv/design/ifu/ifu_mem_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_mem_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ic_mem.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_bp_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_ifc_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_compress_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu/ifu_aln_ctl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/ifu//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/dma_ctrl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/pic_ctrl.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/mem.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design//home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/swerv_wrapper.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/swerv_types.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design//home/travWARNING (42)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/swerv_types.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/swerv_types.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (43)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/global.h::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/global.h) has an unsupported extension (.h), Odin only supports { .v .vh }WARNING (44)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/build.h::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/swerv/design/include/build.h) has an unsupported extension (.h), Odin only supports { .v .vh }ERROR (45)::ARG_ERROR cannot open file: --top_module swerv_wrapperAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_util.cpp]open_file::121
name: ibexdescription: Full ibex core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_compressed_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv']incdirs: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl']should_fail: 0tags: ibextop_module: rc: 0%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:93: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.if_stage_i.if_id_pipe_reg_we%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:93: ibex_core.if_stage_i.if_id_pipe_reg_we%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:171: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:75: ibex_core.if_stage_i.have_instr%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:227: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv:93: ibex_core.if_stage_i.if_id_pipe_reg_we%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:167: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.id_in_ready%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:167: ibex_core.id_in_ready%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:191: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:106: ibex_core.id_stage_i.controller_i.halt_if%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:558: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:167: ibex_core.id_in_ready%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:114: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:47: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mac_res_signed%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:248: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_a%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:51: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:51: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:114: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:47: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mac_res_signed%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:248: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:51: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_a%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:114: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:47: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mac_res_signed%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:248: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:54: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.sign_b%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:52: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:52: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:114: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:47: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mac_res_signed%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:248: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:52: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mult_op_b%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:53: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.accum%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:53: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.accum%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:114: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:47: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.mac_res_signed%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:248: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:53: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.accum%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.multdiv_alu_operand_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: ibex_core.ex_block_i.multdiv_alu_operand_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv:72: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:46: ibex_core.ex_block_i.alu_adder_result_ext%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:130: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:57: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.is_greater_equal%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:121: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:66: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.next_remainder%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:144: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: ibex_core.ex_block_i.multdiv_alu_operand_a%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.ex_block_i.multdiv_alu_operand_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: ibex_core.ex_block_i.multdiv_alu_operand_b%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv:72: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:46: ibex_core.ex_block_i.alu_adder_result_ext%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:130: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:57: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.is_greater_equal%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:121: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:66: ibex_core.ex_block_i.gen_multdiv_fast.multdiv_i.next_remainder%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv:144: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:45: ibex_core.ex_block_i.multdiv_alu_operand_b%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:118: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.lsu_addr_incr_req%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:118: ibex_core.lsu_addr_incr_req%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv:213: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv:183: ibex_core.id_stage_i.alu_op_a_mux_sel%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv:225: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv:205: ibex_core.id_stage_i.alu_operand_a%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv:72: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv:46: ibex_core.ex_block_i.alu_adder_result_ext%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv:313: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv:76: ibex_core.load_store_unit_i.split_misaligned_access%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv:318: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:118: ibex_core.lsu_addr_incr_req%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:130: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.core_ctrl_firstfetch%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:130: ibex_core.core_ctrl_firstfetch%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:276: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:258: ibex_core.clock_en%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv:16: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv:14: ibex_core.core_clock_gate_i.clk_en%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv:22: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:256: ibex_core.clk%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:573: ACTIVE%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:573: ASSIGNPRE%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:98: __Vdly__ibex_core.id_stage_i.controller_i.ctrl_fsm_cs%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:565: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:98: ibex_core.id_stage_i.controller_i.ctrl_fsm_ns%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv:191: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv:130: ibex_core.core_ctrl_firstfetch%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv:149: Signal unoptimizable: Feedback to clock or circular logic: ibex_core.cs_registers_i.mie_q
name: ibexdescription: Full ibex core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_compressed_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv']incdirs: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl']should_fail: 0tags: ibextop_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv' to AST representation.Generating RTLIL representation for module `\prim_clock_gating'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv:16: syntax error, unexpected TOK_ID, expecting TOK_LOCALPARAM or TOK_ENDPACKAGE
name: ibexdescription: Full ibex core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_compressed_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_decoder.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv']incdirs: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl']should_fail: 0tags: ibextop_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (3)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (4)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (5)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (6)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (7)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (8)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (9)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (10)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (11)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv to parse listAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_core.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pmp.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_fetch_fifo.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_prefetch_buffer.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_fast.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_multdiv_slow.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_load_store_unit.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_if_stage.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.sv, trying /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_id_stage.svAdding file /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv to parse listUnable to open /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl//home/travis/build/SymbiFlow/sv-tests/third_party/coWARNING (12)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_ex_block.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (13)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_decoder.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_decoder.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (14)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_cs_registers.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (15)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_controller.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (16)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_compressed_decoder.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_compressed_decoder.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (17)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_alu.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (18)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_pkg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (19)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/examples/sim/rtl/prim_clock_gating.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/ibex/rtl/ibex_register_file_ff.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') * targeting FPGA synthesis or Verilator simulation.ERROR (21)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: fx68kdescription: Full fx68k core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv']should_fail: 0tags: fx68kincdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:467: Operator COND expects 9 bits on the Conditional True, but Conditional True's CONST '4'h6' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:467: Operator COND expects 9 bits on the Conditional False, but Conditional False's CONST '4'h0' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:468: Operator COND expects 5 bits on the Conditional True, but Conditional True's CONST '4'h6' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:468: Operator COND expects 5 bits on the Conditional False, but Conditional False's CONST '4'h0' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional True, but Conditional True's CONST '4'h6' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:472: Operator COND expects 9 bits on the Conditional False, but Conditional False's CONST '4'h0' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional True, but Conditional True's CONST '4'h6' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:473: Operator COND expects 5 bits on the Conditional False, but Conditional False's CONST '4'h0' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:278: Operator ADD expects 17 bits on the LHS, but LHS's REPLICATE generates 9 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:278: Operator ADD expects 17 bits on the RHS, but RHS's REPLICATE generates 9 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:278: Operator ADD expects 17 bits on the RHS, but RHS's VARREF 'cin' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:279: Operator SUB expects 17 bits on the LHS, but LHS's REPLICATE generates 9 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:279: Operator SUB expects 17 bits on the RHS, but RHS's REPLICATE generates 9 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:279: Operator SUB expects 17 bits on the RHS, but RHS's VARREF 'cin' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:284: Operator ADD expects 17 bits on the RHS, but RHS's VARREF 'cin' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:285: Operator SUB expects 17 bits on the RHS, but RHS's VARREF 'cin' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1904: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:41: Unsupported: Unpacked struct/union%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:66: Unsupported: Unpacked struct/union%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:49: Unsupported: Unpacked struct/union%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2371: Operator AND expects 32 bits on the LHS, but LHS's SEL generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2371: Operator AND expects 32 bits on the RHS, but RHS's VARREF 'bcComplete' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2371: Logical Operator IF expects 1 bit on the If, but If's AND generates 32 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2116: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's REPLICATE generates 2 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1815: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1226: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '1'bx' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1231: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '1'bx' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1236: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '1'bx' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1480: Operator ADD expects 16 bits on the RHS, but RHS's SEL generates 1 bits.%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1165: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:1166: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).%Error-BLKANDNBLK: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: Unsupported: Blocked and non-blocking assignments to same variable: fx68k.Nanod%Warning-MULTIDRIVEN: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: Signal has multiple driving blocks with different clocking: fx68k.Nanod%Warning-MULTIDRIVEN: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:874: ... Location of first driving block%Warning-MULTIDRIVEN: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:719: ... Location of other driving block%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:459: Signal unoptimizable: Feedback to clock or circular logic: fx68k.excUnit.alu.aluCorf.htemp%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:459: fx68k.excUnit.alu.aluCorf.htemp%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:463: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:463: fx68k.excUnit.alu.aluCorf.highC%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:465: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv:459: fx68k.excUnit.alu.aluCorf.htemp%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:857: Signal unoptimizable: Feedback to clock or circular logic: fx68k.nDecoder.isPcRel%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:857: fx68k.nDecoder.isPcRel%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:863: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: fx68k.Nanod%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:857: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:857: fx68k.nDecoder.isPcRel%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:151: Signal unoptimizable: Feedback to clock or circular logic: fx68k.Clks%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:151: fx68k.Clks%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2218: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2218: fx68k.busArbiter.__Vsenitemexpr1%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2220: ACTIVE%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2220: ASSIGNPRE%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2160: __Vdly__fx68k.busArbiter.dmaPhase%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:2219: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:151: fx68k.Clks%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:153: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:151: fx68k.Clks%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:276: Signal unoptimizable: Feedback to clock or circular logic: fx68k.Irdecod%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:276: fx68k.Irdecod%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:937: ALWAYS%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:276: fx68k.Irdecod%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: Signal unoptimizable: Feedback to clock or circular logic: fx68k.Nanod%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: fx68k.Nanod%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:766: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv:274: fx68k.Nanod%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv
name: fx68kdescription: Full fx68k core testfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv', '/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv']should_fail: 0tags: fx68kincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (3)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68kAlu.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (4)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/fx68k.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/cores/fx68k/uaddrPla.sv::15 error in parsing: (syntax error, unexpected vLOCALPARAM, expecting vMODULE or preDEFAULT_NETTYPE)`define SRIL1 'h385ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_carryadddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v:5:8: error: identifier 'WIDTH' used before its declarationinput [WIDTH-1:0] a, b; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v:3:11: note: declared hereparameter WIDTH = 8; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v:6:9: error: identifier 'WIDTH' used before its declarationoutput [WIDTH-1:0] y; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v:3:11: note: declared hereparameter WIDTH = 8; ^
name: simple_valuesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:8:8: error: language feature not yet supportedalways @* begin ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:22:8: error: language feature not yet supportedalways @* ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:33:20: warning: vector literal too large for the given number of bits [-Wliteral-overflow] 4'b1001: y = 16'h123abc; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:34:20: warning: vector literal too large for the given number of bits [-Wliteral-overflow] 4'b1010: y = 16'o1234567; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:35:20: warning: vector literal too large for the given number of bits [-Wliteral-overflow] 4'b1011: y = 16'd3456789; ^
name: simple_forgen02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:5:8: error: identifier 'WIDTH' used before its declarationinput [WIDTH-1:0] a, b; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:3:11: note: declared hereparameter WIDTH = 8; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:8:9: error: identifier 'WIDTH' used before its declarationoutput [WIDTH-1:0] y; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:3:11: note: declared hereparameter WIDTH = 8; ^
name: simple_rotatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:20:32: error: language feature not yet supported always @* ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:22:45: error: too many arguments to subroutine call; expected 0 but 2 were provided in[wrap(j, i)] & (shift_amount[i] ^ direction); ^~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:38:1: error: language feature not yet supportedinput integer pos;^~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:39:1: error: language feature not yet supportedinput integer level;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:42:15: error: use of undeclared identifier 'pos' out = pos - (1 << level); ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v:42:27: error: use of undeclared identifier 'level' out = pos - (1 << level); ^~~~~
name: asicworld_code_hdl_models_parity_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v:17:3: error: language feature not yet supported input [31:0] data; ^~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v:27:21: error: too many arguments to subroutine call; expected 0 but 1 were providedassign parity_out = parity(data_in); ^~~~~~
name: asicworld_code_hdl_models_camdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:20:9: error: identifier 'DEPTH' used before its declarationinput [DEPTH-1:0] cam_data_in; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:16:11: note: declared hereparameter DEPTH = 1 << ADDR_WIDTH; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:25:6: error: identifier 'ADDR_WIDTH' used before its declarationreg [ADDR_WIDTH-1:0] cam_addr_out; ^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:15:11: note: declared hereparameter ADDR_WIDTH = 8; ^
name: simple_repwhiledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:4:3: error: language feature not yet supported input [31:0] value; ^~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:7:11: error: use of undeclared identifier 'value' while (value > 0) begin ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:8:5: error: use of undeclared identifier 'value' value = value >> 1; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:8:13: error: use of undeclared identifier 'value' value = value >> 1; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:15:3: error: language feature not yet supported input [7:0] value; ^~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:18:12: error: use of undeclared identifier 'value' repeat (value) ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:29:18: error: too many arguments to subroutine call; expected 0 but 1 were provided y_table[i] <= mylog2(i); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:30:18: error: too many arguments to subroutine call; expected 0 but 1 were provided x_table[i] <= myexp2(i); ^~~~~~
name: simple_macrosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v:23:8: error: language feature not yet supportedalways @* begin ^~
name: simple_usb_phy_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v:14:8: error: language feature not yet supportedalways @* ^~
name: asicworld_code_tidbits_fsm_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:29:21: error: too many arguments to subroutine call; expected 0 but 3 were providedassign next_state = fsm_function(state, req_0, req_1); ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:32:3: error: language feature not yet supported input [SIZE-1:0] state ; ^~~~~~~~~~~~~~~~~~~~~~~~~~ ../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:33:3: error: language feature not yet supported input req_0 ; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:34:3: error: language feature not yet supported input req_1 ; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:60:14: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:62:14: error: language feature not yet supported state <= #1 next_state; ^~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:69:12: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:70:12: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:75:28: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:76:28: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:79:29: error: language feature not yet supported gnt_0 <= #1 1'b1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:80:29: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:83:29: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:84:29: error: language feature not yet supported gnt_1 <= #1 1'b1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:87:30: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v:88:30: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~
name: simple_forloopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v:8:9: error: language feature not yet supported always @* begin ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v:17:9: error: language feature not yet supported always @* begin ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v:21:9: error: language feature not yet supported always @* begin ^~
name: sva_extnetsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:6:9: error: language feature not yet supported always @* assert(o == i); ^~
name: simple_mem2regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:10:8: error: language feature not yet supportedalways @* begin ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:72:3: error: language feature not yet supported input integer depth; ^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:73:17: error: use of undeclared identifier 'depth' depth2Index = depth; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:76:22: error: too many arguments to subroutine call; expected 0 but 1 were provided assign intermediate[depth2Index(1)] = 1; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:77:22: error: too many arguments to subroutine call; expected 0 but 1 were provided assign intermediate[depth2Index(2)] = 2; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:80:32: error: too many arguments to subroutine call; expected 0 but 1 were provided assign result2 = intermediate[depth2Index(2)]; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:81:32: error: too many arguments to subroutine call; expected 0 but 1 were provided assign result3 = intermediate[depth2Index(3)]; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:104:16: error: language feature not yet supported always @* begin ^~
name: sva_basic05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:4:2: error: unknown module 'demo' demo uut ( ^~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:9:16: error: use of undeclared identifier 'uut' assign read = uut.read; ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:10:17: error: use of undeclared identifier 'uut' assign write = uut.write; ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:11:17: error: use of undeclared identifier 'uut' assign ready = uut.ready; ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:13:2: error: language feature not yet supported a_rw: assert property ( @(posedge clock) !(read && write) ); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:17:2: error: language feature not yet supported a_wr: assert property ( @(posedge clock) write |=> ready ); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: asicworld_code_tidbits_fsm_using_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:57:14: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:59:14: error: language feature not yet supported state <= #1 next_state; ^~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:66:12: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:67:12: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:72:28: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:73:28: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:76:29: error: language feature not yet supported gnt_0 <= #1 1'b1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:77:29: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:80:29: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:81:29: error: language feature not yet supported gnt_1 <= #1 1'b1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:84:30: error: language feature not yet supported gnt_0 <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:85:30: error: language feature not yet supported gnt_1 <= #1 1'b0; ^~~~~~~
name: sva_basic02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:12:2: error: language feature not yet supported a_rw: assert property ( @(posedge clock) !(read && write) ); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:16:2: error: language feature not yet supported a_wr: assert property ( @(posedge clock) write |=> ready ); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:20:1: error: expected memberbind top top_properties properties_inst (.*);^~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:20:6: error: use of undeclared identifier 'top'bind top top_properties properties_inst (.*); ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:20:24: error: expected ','bind top top_properties properties_inst (.*); ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:20:41: error: expected declaratorbind top top_properties properties_inst (.*); ^
name: simple_wreducedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v:2:15: error: use of undeclared identifier '$signed' assign x = -$signed({1'b0, a}); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v:3:14: error: use of undeclared identifier '$signed' assign y = $signed({1'b0, a}) + $signed({1'b0, b}); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v:3:35: error: use of undeclared identifier '$signed' assign y = $signed({1'b0, a}) + $signed({1'b0, b}); ^~~~~~~
name: simple_task_funcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:9:1: error: language feature not yet supportedinput [3:0] s1, s2, s3;^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:10:13: error: use of undeclared identifier 's1'sum_shift = s1 + (s2 << 2) + (s3 << 4); ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:10:19: error: use of undeclared identifier 's2'sum_shift = s1 + (s2 << 2) + (s3 << 4); ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:10:31: error: use of undeclared identifier 's3'sum_shift = s1 + (s2 << 2) + (s3 << 4); ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:18:1: error: language feature not yet supportedoutput [7:0] out;^~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:19:1: error: language feature not yet supportedinput [7:0] in;^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:20:1: error: use of undeclared identifier 'out'out = out + in;^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:20:7: error: use of undeclared identifier 'out'out = out + in; ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:20:13: error: use of undeclared identifier 'in'out = out + in; ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:24:6: error: too many arguments to subroutine call; expected 0 but 3 were provided x = sum_shift(a, b, c); ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:25:6: error: too many arguments to subroutine call; expected 0 but 3 were provided y = sum_shift(a[7:4], b[5:2], c[3:0]); ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:26:6: error: too many arguments to subroutine call; expected 0 but 3 were provided z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3); ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:26:40: error: too many arguments to subroutine call; expected 0 but 3 were provided z = sum_shift(a[0], b[5:4], c >> 5) ^ sum_shift(1, 2, 3); ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:29:2: error: too many arguments to subroutine call; expected 0 but 2 were provided add_to(w, x); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:30:2: error: too many arguments to subroutine call; expected 0 but 2 were provided add_to(w, y); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:31:2: error: too many arguments to subroutine call; expected 0 but 2 were provided add_to(w, z); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:72:18: error: too many arguments to subroutine call; expected 0 but 2 were provided assign dout_a = test(din_a,din_b); ^~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:74:3: error: language feature not yet supported input [7:0] a; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:75:3: error: language feature not yet supported input [7:0] b; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:79:15: error: use of undeclared identifier 'a' test[i] = a[i] & b[i]; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:79:22: error: use of undeclared identifier 'b' test[i] = a[i] & b[i]; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:90:3: error: language feature not yet supported input [7:0] i; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:91:3: error: language feature not yet supported parameter p = 42; ^~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:93:12: error: use of undeclared identifier 'i' test1 = i + p; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:97:3: error: language feature not yet supported input [7:0] i; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:98:3: error: language feature not yet supported parameter p2 = p+42; ^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:100:12: error: use of undeclared identifier 'i' test2 = i + p2; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:100:16: error: use of undeclared identifier 'p2' test2 = i + p2; ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:104:3: error: language feature not yet supported input [7:0] i; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:106:12: error: use of undeclared identifier 'i' test3 = i + p; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:110:3: error: language feature not yet supported input [7:0] i; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:111:3: error: language feature not yet supported parameter px = p + 13; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:112:3: error: language feature not yet supported parameter p3 = px - 37; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:113:3: error: language feature not yet supported parameter p4 = p3 ^ px; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:115:12: error: use of undeclared identifier 'i' test4 = i + p4; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:115:16: error: use of undeclared identifier 'p4' test4 = i + p4; ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:118:16: error: too many arguments to subroutine call; expected 0 but 1 were provided assign out1 = test1(in); ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:119:16: error: too many arguments to subroutine call; expected 0 but 1 were provided assign out2 = test2(in); ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:120:16: error: too many arguments to subroutine call; expected 0 but 1 were provided assign out3 = test3(in); ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:121:16: error: too many arguments to subroutine call; expected 0 but 1 were provided assign out4 = test4(in); ^~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:133:3: error: language feature not yet supported output out; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:134:3: error: language feature not yet supported input in; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:135:3: error: use of undeclared identifier 'out' out = in; ^~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:135:9: error: use of undeclared identifier 'in' out = in; ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:139:3: error: too many arguments to subroutine call; expected 0 but 2 were provided myTask(data_out,data_in); ^~~~~~
name: simple_scopesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:3:3: error: language feature not yet supported input [15:0] x, y; ^~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:16:3: error: language feature not yet supported input [15:0] x, y; ^~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:27:3: error: language feature not yet supported input [3:0] a; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:30:8: error: use of undeclared identifier 'a' y = a * 23; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:36:3: error: language feature not yet supported input [3:0] a; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:42:14: error: use of undeclared identifier 'a' x = 77 + a; ^../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:49:9: error: language feature not yet supported always @* begin ^~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:50:7: error: too many arguments to subroutine call; expected 0 but 2 were provided x = func_01(11, 22); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:51:7: error: too many arguments to subroutine call; expected 0 but 2 were provided y = func_02(33, 44); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:52:3: error: too many arguments to subroutine call; expected 0 but 1 were provided task_01(k); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:53:3: error: too many arguments to subroutine call; expected 0 but 1 were provided task_02(k); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:60:7: error: too many arguments to subroutine call; expected 0 but 2 were provided x = func_01(y, x); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:61:7: error: too many arguments to subroutine call; expected 0 but 2 were provided y = func_02(y, x); ^~~~~~~
name: asicworld_code_tidbits_fsm_using_single_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:33:12: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:39:26: error: language feature not yet supported state <= #1 GNT0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:43:26: error: language feature not yet supported state <= #1 GNT1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:45:26: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:48:26: error: language feature not yet supported state <= #1 GNT0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:51:26: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:54:26: error: language feature not yet supported state <= #1 GNT1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:57:26: error: language feature not yet supported state <= #1 IDLE; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v:59:23: error: language feature not yet supported default : state <= #1 IDLE; ^~~~~~~
name: simple_i2c_master_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:14:18: error: language feature not yet supported cmd_stop <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:16:18: error: language feature not yet supported cmd_stop <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:20:12: error: language feature not yet supported al <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:22:12: error: language feature not yet supported al <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:24:12: error: language feature not yet supported al <= #1 ~cmd_stop; ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:43:22: error: language feature not yet supported cnt <= #1 clk_cnt; ^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:44:22: error: language feature not yet supported clk_en <= #1 1'b1; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:48:22: error: language feature not yet supported cnt <= #1 cnt; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:49:22: error: language feature not yet supported clk_en <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:53:27: error: language feature not yet supported cnt <= #1 cnt - 16'h1; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:54:20: error: language feature not yet supported clk_en <= #1 1'b0; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:59:18: error: language feature not yet supported cmd_stop <= #1 cmd; ^~~~~~
name: errors_syntax_err01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v:2:9: error: packed dimensions not allowed on predefined integer type 'integer'integer [31:0]w; ^
name: hana_test_parserdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:7: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:7: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:19: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:33: Unsupported: Multiple top level modules: f4_ahmad and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:33: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:40: Unsupported: Multiple top level modules: f5_test and f4_ahmad%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:40: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:52: Unsupported: Multiple top level modules: f5_ternaryop and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:52: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:61: Unsupported: Multiple top level modules: f5_fulladd4 and f5_ternaryop%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:71: Unsupported: Multiple top level modules: f6_adder and f5_fulladd4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:71: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:79: Unsupported: Multiple top level modules: f7_test and f6_adder%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:79: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_shifterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:9: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:9: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:15: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:15: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:21: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:21: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:27: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:27: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:33: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:33: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:39: Unsupported: Multiple top level modules: f7_test and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:39: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:45: Unsupported: Multiple top level modules: f8_test and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:45: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:51: Unsupported: Multiple top level modules: f9_test and f8_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:51: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:57: Unsupported: Multiple top level modules: f10_test and f9_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v:57: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f10_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_seqdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v:9: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v:9: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Unsupported: Multiple top level modules: DEC2 and DEC1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:176: Unsupported: Multiple top level modules: DEC3 and DEC2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:176: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:19: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:35: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:35: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:51: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:51: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:70: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:70: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:99: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:99: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:144: Unsupported: Multiple top level modules: f7_test and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:144: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:27: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:27: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:37: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:78: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:78: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:90: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:90: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:163: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:163: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_incdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:10: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:10: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:17: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:17: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:24: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:24: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:31: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:38: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v:38: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_techmap_techdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:7: Unsupported: Multiple top level modules: f1_TECH_AND4 and f1_TECH_AND18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:7: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:12: Unsupported: Multiple top level modules: f2_TECH_AND5 and f1_TECH_AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:12: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:17: Unsupported: Multiple top level modules: f3_TECH_NAND18 and f2_TECH_AND5%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:17: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:21: Unsupported: Multiple top level modules: f3_TECH_NAND4 and f3_TECH_NAND18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:21: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:25: Unsupported: Multiple top level modules: f3_TECH_NAND2 and f3_TECH_NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:30: Unsupported: Multiple top level modules: f4_TECH_NAND18 and f3_TECH_NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:30: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:34: Unsupported: Multiple top level modules: f4_TECH_NAND4 and f4_TECH_NAND18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:34: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:38: Unsupported: Multiple top level modules: f4_TECH_NAND2 and f4_TECH_NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:38: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:43: Unsupported: Multiple top level modules: f5_TECH_NAND18 and f4_TECH_NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:47: Unsupported: Multiple top level modules: f5_TECH_NAND4 and f5_TECH_NAND18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:47: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:51: Unsupported: Multiple top level modules: f5_TECH_NAND2 and f5_TECH_NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:51: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:56: Unsupported: Multiple top level modules: f6_TECH_NOR18 and f5_TECH_NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:56: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:60: Unsupported: Multiple top level modules: f6_TECH_NOR4 and f6_TECH_NOR18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:60: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:64: Unsupported: Multiple top level modules: f6_TECH_NOR2 and f6_TECH_NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:64: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:69: Unsupported: Multiple top level modules: f7_TECH_NOR18 and f6_TECH_NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:69: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:73: Unsupported: Multiple top level modules: f7_TECH_NOR4 and f7_TECH_NOR18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:73: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:77: Unsupported: Multiple top level modules: f7_TECH_NOR2 and f7_TECH_NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:77: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:82: Unsupported: Multiple top level modules: f8_TECH_NOR18 and f7_TECH_NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:82: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:86: Unsupported: Multiple top level modules: f8_TECH_NOR4 and f8_TECH_NOR18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:90: Unsupported: Multiple top level modules: f8_TECH_NOR2 and f8_TECH_NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:90: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:95: Unsupported: Multiple top level modules: f9_TECH_OR18 and f8_TECH_NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:95: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:99: Unsupported: Multiple top level modules: f9_TECH_OR4 and f9_TECH_OR18%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:99: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:104: Unsupported: Multiple top level modules: f10_TECH_OR5 and f9_TECH_OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:109: Unsupported: Multiple top level modules: f11_TECH_XOR5 and f10_TECH_OR5%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:109: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:112: Unsupported: Multiple top level modules: f11_TECH_XOR2 and f11_TECH_XOR5%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v:112: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_sopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:13: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:25: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:41: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:41: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:48: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:48: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:53: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:53: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:58: Unsupported: Multiple top level modules: f7_test and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:58: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:63: Unsupported: Multiple top level modules: f8_test and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:63: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f8_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_xnordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_intermoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:18: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:30: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:30: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:41: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:41: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:54: Unsupported: Multiple top level modules: f5_NonBlockingEx and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:54: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:71: Unsupported: Multiple top level modules: f6_FlipFlop and f5_NonBlockingEx%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:71: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:84: Unsupported: Multiple top level modules: f7_FlipFlop and f6_FlipFlop%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:84: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:99: Unsupported: Multiple top level modules: f8_inc and f7_FlipFlop%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:99: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:108: Unsupported: Multiple top level modules: f9_NegEdgeClock and f8_inc%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:108: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:121: Unsupported: Multiple top level modules: f10_MyCounter and f9_NegEdgeClock%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:121: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:137: Unsupported: Multiple top level modules: f11_test and f10_MyCounter%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:137: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:148: Unsupported: Multiple top level modules: f12_test and f11_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:148: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:154: Unsupported: Multiple top level modules: f13_test and f12_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:154: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:163: Unsupported: Multiple top level modules: f14_test and f13_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:163: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:187: Unsupported: Multiple top level modules: f15_test and f14_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:187: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:222: Unsupported: Multiple top level modules: f16_test and f15_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:222: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:234: Unsupported: Multiple top level modules: f17_test and f16_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:234: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:249: Unsupported: Multiple top level modules: f18_test and f17_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:249: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:256: Unsupported: Multiple top level modules: f19_buffer and f18_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:256: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:267: Unsupported: Multiple top level modules: f20_test and f19_buffer%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:267: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:280: Unsupported: Multiple top level modules: f21_test and f20_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:280: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:291: Unsupported: Multiple top level modules: f22_test and f21_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:291: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:305: Unsupported: Multiple top level modules: f23_test and f22_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:305: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:314: Unsupported: Multiple top level modules: f24_test and f23_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:314: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:326: Unsupported: Multiple top level modules: f25_test and f24_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:326: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:335: Unsupported: Multiple top level modules: f26_test and f25_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:335: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_xordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_bufferdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v:14: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v:14: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Unsupported: Multiple top level modules: DEC2 and DEC1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_parse2synthtransdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:27: Unsupported: Multiple top level modules: f2_demultiplexer1_to_4 and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:27: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:55: Unsupported: Multiple top level modules: f3_test and f2_demultiplexer1_to_4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:64: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:64: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:68: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:68: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:81: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:81: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:90: Unsupported: Multiple top level modules: f7_test and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:90: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:98: Unsupported: Multiple top level modules: f8_test and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:109: Unsupported: Multiple top level modules: f9_test and f8_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:109: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f9_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_nanddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:23: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v:23: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_anddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:23: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:23: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:28: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:28: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:33: Unsupported: Multiple top level modules: f7_test and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v:33: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f7_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:10: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:10: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:25: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:37: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:50: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:50: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:57: Unsupported: Multiple top level modules: f6_NonBlockingEx and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:57: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:74: Unsupported: Multiple top level modules: f7_FlipFlop and f6_NonBlockingEx%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:87: Unsupported: Multiple top level modules: f8_inc and f7_FlipFlop%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:87: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:96: Unsupported: Multiple top level modules: f9_MyCounter and f8_inc%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:96: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:112: Unsupported: Multiple top level modules: f10_FlipFlop and f9_MyCounter%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:112: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:127: Unsupported: Multiple top level modules: f11_test and f10_FlipFlop%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:127: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f11_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_nordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_techmapdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:23: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:23: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:159: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:159: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_vlibdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v:16: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v:16: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Unsupported: Multiple top level modules: XNOR4 and XNOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:142: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Unsupported: Multiple top level modules: DEC1 and XNOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:148: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Unsupported: Multiple top level modules: DEC2 and DEC1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:161: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:176: Unsupported: Multiple top level modules: DEC3 and DEC2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:176: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:195: Unsupported: Multiple top level modules: DEC4 and DEC3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:195: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:221: Unsupported: Multiple top level modules: DEC5 and DEC4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:221: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: hana_test_simulation_ordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:8: Unsupported: Multiple top level modules: f2_test and f1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:8: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:13: Unsupported: Multiple top level modules: f3_test and f2_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:18: Unsupported: Multiple top level modules: f4_test and f3_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:23: Unsupported: Multiple top level modules: f5_test and f4_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:23: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:28: Unsupported: Multiple top level modules: f6_test and f5_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v:28: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Unsupported: Multiple top level modules: BUF and f6_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:19: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Unsupported: Multiple top level modules: TRIBUF and BUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:25: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Unsupported: Multiple top level modules: INV and TRIBUF%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Unsupported: Multiple top level modules: AND2 and INV%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:37: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Unsupported: Multiple top level modules: AND3 and AND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Unsupported: Multiple top level modules: AND4 and AND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:49: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Unsupported: Multiple top level modules: OR2 and AND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:55: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Unsupported: Multiple top level modules: OR3 and OR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:61: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Unsupported: Multiple top level modules: OR4 and OR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:67: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Unsupported: Multiple top level modules: NAND2 and OR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:74: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Unsupported: Multiple top level modules: NAND3 and NAND2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:80: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Unsupported: Multiple top level modules: NAND4 and NAND3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Unsupported: Multiple top level modules: NOR2 and NAND4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:92: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Unsupported: Multiple top level modules: NOR3 and NOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:98: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Unsupported: Multiple top level modules: NOR4 and NOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:104: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Unsupported: Multiple top level modules: XOR2 and NOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:111: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Unsupported: Multiple top level modules: XOR3 and XOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:117: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Unsupported: Multiple top level modules: XOR4 and XOR3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:123: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Unsupported: Multiple top level modules: XNOR2 and XOR4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:130: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Unsupported: Multiple top level modules: XNOR3 and XNOR2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:136: Fix, or use --top-module option to select which you want.%Error: Exiting due to too many errors encountered; --error-limit=50%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v
name: asicworld_code_verilog_tutorial_decoder_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-CASEINCOMPLETE: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v:9: Case values incompletely covered (example pattern 0x0)%Warning-CASEINCOMPLETE: Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
name: errors_syntax_err05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v:2: Input/output/inout does not appear in port list: x%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v
name: simple_attrib09_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-COMBDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v:13: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).%Warning-COMBDLY: Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.%Warning-COMBDLY: *** See the manual before disabling this,%Warning-COMBDLY: else you may end up with different sim results.
name: asicworld_code_verilog_tutorial_fsm_full_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:10: Define or directive not defined: `outfile%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:10: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:18: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:19: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:20: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:21: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:22: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:23: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:24: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:25: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:26: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:27: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:28: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:36: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:38: Unsupported: Ignoring delay on this delayed statement.%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
name: simple_valuesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:33: Too many digits for 16 bit number: 16'h123abc%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:35: Value too large for 16 bit number: 3456789%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v
name: simple_forgen02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:12: Signal unoptimizable: Feedback to clock or circular logic: uut_forgen02.carry%Warning-UNOPTFLAT: Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:12: uut_forgen02.carry%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:21: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:16: uut_forgen02.adder[1].D%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:24: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v:12: uut_forgen02.carry
name: asicworld_code_hdl_models_arbiter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:22: Define or directive not defined: `outfile%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:22: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:23: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:25: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:27: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:29: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:32: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:35: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:38: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:40: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:42: syntax error, unexpected '@'%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:43: Unsupported: Ignoring delay on this delayed statement.%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v
name: simple_processdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v:21: Unsupported: Multiple top level modules: uut and blocking_cond%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v:21: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v:61: Unsupported: Multiple top level modules: uart and uut%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v:61: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v
name: asicworld_code_verilog_tutorial_first_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:9: Define or directive not defined: `outfile%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:9: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:11: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:12: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:14: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:15: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:24: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:26: Unsupported: Ignoring delay on this delayed statement.%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v
name: simple_dff_initdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:11: Unsupported: Multiple top level modules: dff1_test and dff0_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:11: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:22: Unsupported: Multiple top level modules: dff0a_test and dff1_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:22: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:33: Unsupported: Multiple top level modules: dff1a_test and dff0a_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:33: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:44: Unsupported: Multiple top level modules: dff_test_997 and dff1a_test%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v:44: Fix, or use --top-module option to select which you want.%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v
name: simple_mem_arstdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v:26: Operator ASSIGNDLY expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: simple_vloghammerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:11: Unsupported: Multiple top level modules: test02 and test01%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:11: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:17: Unsupported: Multiple top level modules: test03 and test02%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:17: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:24: Unsupported: Multiple top level modules: test04 and test03%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:24: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:46: Unsupported: Multiple top level modules: test07 and test04%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:46: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:53: Unsupported: Multiple top level modules: test08 and test07%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:53: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:60: Unsupported: Multiple top level modules: test09 and test08%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:60: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:68: Unsupported: Multiple top level modules: test10 and test09%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v:68: Fix, or use --top-module option to select which you want.%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v
name: svinterfaces_svinterface_at_topdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv:10: Unsupported: Interfaced port on top level module%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv:109: Can't find definition of scope/variable: u_MyInterfaceFromTop%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv
name: asicworld_code_hdl_models_mux_2to1_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-IMPLICIT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:13: Signal definition not found, creating implicitly: inv_sel%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.%Warning-IMPLICIT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:14: Signal definition not found, creating implicitly: asel%Warning-IMPLICIT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:15: Signal definition not found, creating implicitly: bsel
name: asicworld_code_hdl_models_parity_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v:27: Operator FUNCREF 'parity' expects 32 bits on the Function Argument, but Function Argument's VARREF 'data_in' generates 8 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: asicworld_code_hdl_models_camdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:40: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: asicworld_code_specman_switch_fabricdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:38: Input port connection 'data_in_valid' expects 1 bits on the pin connection, but pin connection's VARREF 'data_in_valid3' generates 8 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:39: Output port connection 'data_out_ack' expects 1 bits on the pin connection, but pin connection's VARREF 'data_out_ack3' generates 8 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:42: Input port connection 'data_in_valid' expects 1 bits on the pin connection, but pin connection's VARREF 'data_in_valid4' generates 8 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:43: Output port connection 'data_out_ack' expects 1 bits on the pin connection, but pin connection's VARREF 'data_out_ack4' generates 8 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:46: Input port connection 'data_in_valid' expects 1 bits on the pin connection, but pin connection's VARREF 'data_in_valid5' generates 8 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:47: Output port connection 'data_out_ack' expects 1 bits on the pin connection, but pin connection's VARREF 'data_out_ack5' generates 8 bits.
name: simple_repwhiledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:18: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'value' generates 8 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:30: Operator FUNCREF 'myexp2' expects 8 bits on the Function Argument, but Function Argument's VARREF 'i' generates 32 bits.%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:29: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v:30: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).
name: simple_macrosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v:18: Unsupported: Multiple top level modules: test_ifdef and test_def%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v:18: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v:240: Unsupported: Multiple top level modules: test_comment_in_macro and test_ifdef%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v:240: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v
name: simple_partseldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v:7: Unsupported: Multiple top level modules: partsel_test002 and partsel_test001%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v:7: Fix, or use --top-module option to select which you want.%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v
name: sva_sva_notdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv:22: syntax error, unexpected assert%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv
name: simple_muxtreedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v:56: Unsupported: Multiple top level modules: default_cases and usb_tx_phy%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v:56: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v:76: Unsupported: Multiple top level modules: select_leaves and default_cases%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v:76: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v
name: simple_dff_different_stylesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:9: Unsupported: Multiple top level modules: dffa and dff%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:9: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:20: Unsupported: Multiple top level modules: dffa1 and dffa%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:20: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:31: Unsupported: Multiple top level modules: dffa2 and dffa1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:31: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:42: Unsupported: Multiple top level modules: dffa3 and dffa2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:42: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:53: Unsupported: Multiple top level modules: dffa4 and dffa3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:53: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:72: Unsupported: Multiple top level modules: dffsr1 and dffa4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:72: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:83: Unsupported: Multiple top level modules: dffsr2 and dffsr1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v:83: Fix, or use --top-module option to select which you want.%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v
name: simple_subbytesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:67: Logical Operator IF expects 1 bit on the If, but If's VARREF 'state' generates 2 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: simple_fiedler-cooleydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v:16: Operator SUB expects 10 bits on the RHS, but RHS's CONST '3'h5' generates 3 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v:17: Operator ADD expects 10 bits on the RHS, but RHS's CONST '2'h3' generates 2 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v:21: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS's VARREF 'cnt_dn' generates 10 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v:22: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS's VARREF 'cnt_up' generates 10 bits.
name: simple_constmuldivmoddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v:3: Operator CASE expects 32 or 4 bits on the Case expression, but Case expression's VARREF 'mode' generates 3 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: asicworld_code_hdl_models_d_ff_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-UNOPT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:3: Signal unoptimizable: Feedback to public clock or circular logic: q%Warning-UNOPT: Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message.%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:3: q%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:26: ASSIGNW%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:3: q_bar%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:25: ASSIGNW%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:3: q%Warning-UNOPTFLAT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:6: Signal unoptimizable: Feedback to clock or circular logic: d_ff_gates.dn%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:6: d_ff_gates.dn%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:15: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:5: d_ff_gates.q_bar_n%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:14: ASSIGNW%Warning-UNOPTFLAT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v:6: d_ff_gates.dn
name: sva_basic00description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv:9: syntax error, unexpected assert, expecting cover%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv:10: Unsupported or unknown PLI call: $sampled%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv
name: errors_syntax_err09description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v:1: Unsupported: Default value on module input: x%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v
name: simple_multiplierdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v:77: Unsupported: Multiple top level modules: Multiplier_2D and Multiplier_flat%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v:77: Fix, or use --top-module option to select which you want.%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v
name: asicworld_code_hdl_models_d_latch_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-UNOPT: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:3: Signal unoptimizable: Feedback to public clock or circular logic: q_bar%Warning-UNOPT: Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message.%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:3: q_bar%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:12: ASSIGNW%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:3: q%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:13: ASSIGNW%Warning-UNOPT: Example path: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v:3: q_bar
name: simple_signedexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v:9: Operator ADD expects 4 bits on the LHS, but LHS's VARREF 'a' generates 2 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v:10: Operator ADD expects 4 bits on the LHS, but LHS's VARREF 'a' generates 2 bits.
name: simple_forloopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v:15: Unsupported: Multiple top level modules: forloops02 and forloops01%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v:15: Fix, or use --top-module option to select which you want.%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v
name: simple_mem2regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:22: Unsupported: Multiple top level modules: mem2reg_test2 and mem2reg_test1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:22: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:53: Unsupported: Multiple top level modules: mem2reg_test3 and mem2reg_test2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:53: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:64: Unsupported: Multiple top level modules: mem2reg_test4 and mem2reg_test3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:64: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:86: Unsupported: Multiple top level modules: mem2reg_test5 and mem2reg_test4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:97: Unsupported: Multiple top level modules: mem2reg_test6 and mem2reg_test5%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:97: Fix, or use --top-module option to select which you want.%Error: Exiting due to 10 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v
name: errors_syntax_err08description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v:4: syntax error, unexpected INTEGER NUMBER, expecting ',' or ';'%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v
name: simple_generatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:43: Unsupported: Multiple top level modules: gen_test2 and gen_test1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:43: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:70: Unsupported: Multiple top level modules: gen_test3 and gen_test2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:70: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:97: Unsupported: Multiple top level modules: gen_test4 and gen_test3%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:97: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:118: Unsupported: Multiple top level modules: gen_test5 and gen_test4%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:118: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:154: Unsupported: Multiple top level modules: gen_test6 and gen_test5%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:154: Fix, or use --top-module option to select which you want.%Error: Exiting due to 10 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v
name: simple_constpowerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v:10: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's POWSS generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v:11: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's POW generates 32 bits.
name: sva_sva_throughoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv:7: syntax error, unexpected assert%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: throughout%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: Exiting due to 4 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv
name: sva_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:12: syntax error, unexpected disable, expecting clocking%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:14: Unsupported or unknown PLI call: $past%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:15: Unsupported or unknown PLI call: $past%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:16: Unsupported or unknown PLI call: $past%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:21: Unsupported or unknown PLI call: $past%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:22: Unsupported or unknown PLI call: $past%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:25: Unsupported or unknown PLI call: $past%Error: Exiting due to 8 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv
name: simple_wreducedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v:7: Unsupported: Multiple top level modules: wreduce_test1 and wreduce_test0%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v:7: Fix, or use --top-module option to select which you want.%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v
name: simple_task_funcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:38: Unsupported: Multiple top level modules: task_func_test02 and task_func_test01%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:38: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:71: Unsupported: Multiple top level modules: task_func_test03 and task_func_test02%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:71: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:86: Unsupported: Multiple top level modules: task_func_test04 and task_func_test03%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:86: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:127: Unsupported: Multiple top level modules: task_func_test05 and task_func_test04%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v:127: Fix, or use --top-module option to select which you want.%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v
name: memories_issue00335description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v:18: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).%Warning-INITIALDLY: Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
name: asicworld_code_verilog_tutorial_v2k_regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the LHS, but LHS's VARREF 'a_in' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the RHS, but RHS's VARREF 'b_in' generates 1 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v:20: Operator ADD expects 8 bits on the RHS, but RHS's VARREF 'c_in' generates 1 bits.
name: sva_sva_rangedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv:7: syntax error, unexpected assert%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: until%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: Exiting due to 4 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv
name: simple_scopesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:42: Operator ADD expects 32 or 16 bits on the RHS, but RHS's VARREF 'a' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v:57: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'k' generates 4 bits.
name: simple_paramodsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:14: Unsupported: Multiple top level modules: pm_test2 and pm_test1%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:14: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:26: Unsupported: Multiple top level modules: pm_test3 and pm_test2%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:26: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v
name: simple_hierarchydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v:19: Operator VAR 'd' expects 8 bits on the Initial value, but Initial value's CONST '3'h7' generates 3 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v:22: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v:23: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'b' generates 4 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v:24: Operator ASSIGNW expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'c' generates 3 bits.
name: errors_syntax_err06description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 0%Warning-ENDLABEL: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v:4: End label 'label2' does not match begin label 'label1'%Warning-ENDLABEL: Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.
name: asicworld_code_verilog_tutorial_multiplydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v:6: Operator SHIFTL expects 5 bits on the LHS, but LHS's VARREF 'a' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: asicworld_code_verilog_tutorial_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:30: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:30: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:31: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:34: Define or directive not defined: `outfile%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:34: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:37: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:40: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:43: syntax error, unexpected $fdisplay%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:46: syntax error, unexpected $fdisplay%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:54: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:58: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:62: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:65: syntax error, unexpected ->%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:69: syntax error, unexpected ->%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:69: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:75: syntax error, unexpected '@'%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:78: syntax error, unexpected ->%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:78: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:97: syntax error, unexpected ->%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:97: Unsupported: Ignoring delay on this delayed statement.%Error: Exiting due to 16 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v
name: asicworld_code_verilog_tutorial_simple_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0%Warning-COMBDLY: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v:8: Delayed assignments (<=) in non-clocked (non flop or latch) block; suggest blocking assignments (=).%Warning-COMBDLY: Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.%Warning-COMBDLY: *** See the manual before disabling this,%Warning-COMBDLY: else you may end up with different sim results.
name: errors_syntax_err04description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v:2: syntax error, unexpected ']', expecting ':'%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v
name: errors_syntax_err10description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v:2: syntax error, unexpected '[', expecting IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v
name: simple_i2c_master_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:29: Unsupported: Multiple top level modules: i2c_test02 and i2c_test01%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v:29: Fix, or use --top-module option to select which you want.%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v
name: errors_syntax_err01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v:2: syntax error, unexpected '[', expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v
name: simple_realexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:15: Unsupported: Multiple top level modules: demo_002 and demo_001%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:15: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:30: Unsupported: Multiple top level modules: demo_004 and demo_002%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:30: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v
name: simple_wandwordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v:3: Unsupported: Verilog 1995 reserved word not implemented: wor%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v:4: Unsupported: Verilog 1995 reserved word not implemented: wand%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v:15: Unsupported: Verilog 1995 reserved word not implemented: wor%Error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v:16: Unsupported: Verilog 1995 reserved word not implemented: wand%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v
name: hana_test_parserdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_ahmad'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f5_ternaryop'.Generating RTLIL representation for module `\f5_fulladd4'.Generating RTLIL representation for module `\f6_adder'.Generating RTLIL representation for module `\f7_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_shifterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Generating RTLIL representation for module `\f7_test'.Generating RTLIL representation for module `\f8_test'.Generating RTLIL representation for module `\f9_test'.Generating RTLIL representation for module `\f10_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_seqdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:5 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:21 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:37 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:53 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f5_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:72 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f6_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:101 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f7_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v:146 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:5 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:29 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:39 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:80 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f5_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:92 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f6_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v:165 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_incdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_techmap_techdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v' to AST representation.Generating RTLIL representation for module `\f1_TECH_AND18'.Generating RTLIL representation for module `\f1_TECH_AND4'.Generating RTLIL representation for module `\f2_TECH_AND5'.Generating RTLIL representation for module `\f3_TECH_NAND18'.Generating RTLIL representation for module `\f3_TECH_NAND4'.Generating RTLIL representation for module `\f3_TECH_NAND2'.Generating RTLIL representation for module `\f4_TECH_NAND18'.Generating RTLIL representation for module `\f4_TECH_NAND4'.Generating RTLIL representation for module `\f4_TECH_NAND2'.Generating RTLIL representation for module `\f5_TECH_NAND18'.Generating RTLIL representation for module `\f5_TECH_NAND4'.Generating RTLIL representation for module `\f5_TECH_NAND2'.Generating RTLIL representation for module `\f6_TECH_NOR18'.Generating RTLIL representation for module `\f6_TECH_NOR4'.Generating RTLIL representation for module `\f6_TECH_NOR2'.Generating RTLIL representation for module `\f7_TECH_NOR18'.Generating RTLIL representation for module `\f7_TECH_NOR4'.Generating RTLIL representation for module `\f7_TECH_NOR2'.Generating RTLIL representation for module `\f8_TECH_NOR18'.Generating RTLIL representation for module `\f8_TECH_NOR4'.Generating RTLIL representation for module `\f8_TECH_NOR2'.Generating RTLIL representation for module `\f9_TECH_OR18'.Generating RTLIL representation for module `\f9_TECH_OR4'.Generating RTLIL representation for module `\f10_TECH_OR5'.Generating RTLIL representation for module `\f11_TECH_XOR5'.Generating RTLIL representation for module `\f11_TECH_XOR2'.Generating RTLIL representation for module `\f12_TECH_XOR5'.Generating RTLIL representation for module `\f12_TECH_XOR2'.Generating RTLIL representation for module `\f13_TECH_XOR2'.Generating RTLIL representation for module `\f14_TECH_XOR5'.Generating RTLIL representation for module `\f14_TECH_XOR2'.Generating RTLIL representation for module `\f15_TECH_XOR5'.Generating RTLIL representation for module `\f15_TECH_XOR2'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_sopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:5 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:15 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v:27 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Generating RTLIL representation for module `\f7_test'.Generating RTLIL representation for module `\f8_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_xnordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_intermoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:286)Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:287)Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:8 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:22 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:34 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:46 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f5_NonBlockingEx'.Generating RTLIL representation for module `\f6_FlipFlop'.Generating RTLIL representation for module `\f7_FlipFlop'.Generating RTLIL representation for module `\f8_inc'.Generating RTLIL representation for module `\f9_NegEdgeClock'.Generating RTLIL representation for module `\f10_MyCounter'.Generating RTLIL representation for module `\f11_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v:142 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f12_test'.Generating RTLIL representation for module `\f13_test'.Generating RTLIL representation for module `\f14_test'.Generating RTLIL representation for module `\f14_mybuf'.Generating RTLIL representation for module `\f15_test'.Generating RTLIL representation for module `\f15_mybuf'.Generating RTLIL representation for module `\f16_test'.Generating RTLIL representation for module `\f17_test'.Generating RTLIL representation for module `\f18_test'.Generating RTLIL representation for module `\f19_buffer'.Generating RTLIL representation for module `\f20_test'.Generating RTLIL representation for module `\f21_test'.Generating RTLIL representation for module `\f22_test'.Generating RTLIL representation for module `\f23_test'.Generating RTLIL representation for module `\f24_test'.Generating RTLIL representation for module `\f25_test'.Generating RTLIL representation for module `\f26_test'.Generating RTLIL representation for module `\f27_test'.Generating RTLIL representation for module `\f28_test'.Generating RTLIL representation for module `\f29_Reduction'.Generating RTLIL representation for module `\f30_test'.Generating RTLIL representation for module `\f31_test'.Generating RTLIL representation for module `\f32_test'.Generating RTLIL representation for module `\f33_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_xordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_bufferdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_parse2synthtransdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:13 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_demultiplexer1_to_4'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:34 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v:46 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Generating RTLIL representation for module `\f7_test'.Generating RTLIL representation for module `\f8_test'.Generating RTLIL representation for module `\f9_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_nanddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_anddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Generating RTLIL representation for module `\f7_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:5 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f2_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:15 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:29 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:42 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f5_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:52 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f6_NonBlockingEx'.Generating RTLIL representation for module `\f7_FlipFlop'.Generating RTLIL representation for module `\f8_inc'.Generating RTLIL representation for module `\f9_MyCounter'.Generating RTLIL representation for module `\f10_FlipFlop'.Generating RTLIL representation for module `\f11_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v:129 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_nordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_techmapdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:15 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f4_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:25 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\f5_test'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v:161 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_vlibdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: hana_test_simulation_ordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v' to AST representation.Generating RTLIL representation for module `\f1_test'.Generating RTLIL representation for module `\f2_test'.Generating RTLIL representation for module `\f3_test'.Generating RTLIL representation for module `\f4_test'.Generating RTLIL representation for module `\f5_test'.Generating RTLIL representation for module `\f6_test'.Successfully finished Verilog frontend.2. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:27)ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v:1097: syntax error, unexpected TOK_SUPPLY1
name: asicworld_code_verilog_tutorial_decoder_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v' to AST representation.Generating RTLIL representation for module `\decoder_always'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v:6 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_lfsr_updowndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr_updown.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr_updown.v' to AST representation.Generating RTLIL representation for module `\lfsr_updown'.Successfully finished Verilog frontend.
name: errors_syntax_err05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v:2: Syntax error.
name: simple_attrib09_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v' to AST representation.Generating RTLIL representation for module `\bar'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v:7 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_encoder_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v' to AST representation.Generating RTLIL representation for module `\encoder_using_if'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v:20 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_bus_condescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_bus_con.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_bus_con.v' to AST representation.Generating RTLIL representation for module `\bus_con'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_uartdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_uart.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_uart.v' to AST representation.Generating RTLIL representation for module `\uart'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_mux_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_case.v' to AST representation.Generating RTLIL representation for module `\mux_using_case'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_case.v:20 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_fsm_full_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v:10: Unimplemented compiler directive or undefined macro `outfile.
name: memories_read_two_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/read_two_mux.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/read_two_mux.v' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: simple_carryadddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v' to AST representation.Generating RTLIL representation for module `\carryadd'.Successfully finished Verilog frontend.
name: simple_valuesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v' to AST representation.Warning: Literal has a width of 16 bit, but value requires 21 bit. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:33)Warning: Literal has a width of 16 bit, but value requires 19 bit. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:34)Warning: Literal has a width of 16 bit, but value requires 22 bit. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:35)Generating RTLIL representation for module `\test_signed'.Generating RTLIL representation for module `\test_const'.Successfully finished Verilog frontend.
name: simple_forgen02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v' to AST representation.Generating RTLIL representation for module `\uut_forgen02'.Successfully finished Verilog frontend.
name: memories_simple_sram_byte_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/simple_sram_byte_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/simple_sram_byte_en.v' to AST representation.Generating RTLIL representation for module `\generic_sram_byte_en'.Successfully finished Verilog frontend.
name: simple_attrib02_port_decldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v' to AST representation.Generating RTLIL representation for module `\bar'.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_arbiter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v:22: Unimplemented compiler directive or undefined macro `outfile.
name: simple_processdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v' to AST representation.Generating RTLIL representation for module `\blocking_cond'.Generating RTLIL representation for module `\uut'.Generating RTLIL representation for module `\uart'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_first_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v:9: Unimplemented compiler directive or undefined macro `outfile.
name: simple_always02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always02.v' to AST representation.Generating RTLIL representation for module `\uut_always02'.Successfully finished Verilog frontend.
name: memories_issue00710description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00710.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00710.v' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_arbiterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter.v' to AST representation.Generating RTLIL representation for module `\arbiter'.Successfully finished Verilog frontend.
name: simple_rotatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v' to AST representation.Generating RTLIL representation for module `\a23_barrel_shift_fpga_rotate'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_nonblockingdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_nonblocking.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_nonblocking.v' to AST representation.Generating RTLIL representation for module `\nonblocking'.Successfully finished Verilog frontend.
name: simple_dff_initdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v' to AST representation.Generating RTLIL representation for module `\dff0_test'.Generating RTLIL representation for module `\dff1_test'.Generating RTLIL representation for module `\dff0a_test'.Generating RTLIL representation for module `\dff1a_test'.Generating RTLIL representation for module `\dff_test_997'.Successfully finished Verilog frontend.
name: simple_attrib03_parameterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib03_parameter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib03_parameter.v:4: syntax error, unexpected TOK_PARAMETER
name: asicworld_code_verilog_tutorial_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder.v' to AST representation.Generating RTLIL representation for module `\decoder'.Successfully finished Verilog frontend.
name: simple_mem_arstdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v' to AST representation.Generating RTLIL representation for module `\MyMem'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_encoder_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_case.v' to AST representation.Generating RTLIL representation for module `\encoder_using_case'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_case.v:18 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: simple_vloghammerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v' to AST representation.Generating RTLIL representation for module `\test01'.Generating RTLIL representation for module `\test02'.Generating RTLIL representation for module `\test03'.Generating RTLIL representation for module `\test04'.Generating RTLIL representation for module `\test07'.Generating RTLIL representation for module `\test08'.Generating RTLIL representation for module `\test09'.Generating RTLIL representation for module `\test10'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_simple_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_function.v' to AST representation.Generating RTLIL representation for module `\simple_function'.Successfully finished Verilog frontend.
name: svinterfaces_svinterface_at_topdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv:10: syntax error, unexpected '.', expecting ',' or '=' or ')'
name: asicworld_code_hdl_models_mux_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v' to AST representation.Generating RTLIL representation for module `\mux_using_if'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v:20 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_mux_2to1_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v' to AST representation.Generating RTLIL representation for module `\mux_2to1_gates'.Warning: Identifier `\inv_sel' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:13.Warning: Identifier `\asel' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:14.Warning: Identifier `\bsel' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v:15.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_parity_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v' to AST representation.Generating RTLIL representation for module `\parity_using_function'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_camdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v' to AST representation.Generating RTLIL representation for module `\cam'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v:32 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_flip_flopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_flip_flop.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_flip_flop.v' to AST representation.Generating RTLIL representation for module `\flif_flop'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_clk_divdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div.v' to AST representation.Generating RTLIL representation for module `\clk_div'.Successfully finished Verilog frontend.
name: asicworld_code_specman_switch_fabricdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v' to AST representation.Generating RTLIL representation for module `\switch_fabric'.Generating RTLIL representation for module `\switch'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_parity_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_assign.v' to AST representation.Generating RTLIL representation for module `\parity_using_assign'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_lfsrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr.v' to AST representation.Generating RTLIL representation for module `\lfsr'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_dff_sync_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_sync_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_sync_reset.v' to AST representation.Generating RTLIL representation for module `\dff_sync_reset'.Successfully finished Verilog frontend.
name: memories_implicit_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/implicit_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/implicit_en.v' to AST representation.Generating RTLIL representation for module `\test'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_rom_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_rom_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_rom_using_case.v' to AST representation.Generating RTLIL representation for module `\rom_using_case'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_rom_using_case.v:20 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_mux_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_assign.v' to AST representation.Generating RTLIL representation for module `\mux_using_assign'.Successfully finished Verilog frontend.
name: simple_repwhiledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v' to AST representation.Generating RTLIL representation for module `\repwhile_test001'.Successfully finished Verilog frontend.
name: simple_macrosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v' to AST representation.Generating RTLIL representation for module `\test_def'.Generating RTLIL representation for module `\test_ifdef'.Generating RTLIL representation for module `\test_comment_in_macro'.Successfully finished Verilog frontend.
name: simple_partseldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v' to AST representation.Generating RTLIL representation for module `\partsel_test001'.Generating RTLIL representation for module `\partsel_test002'.Successfully finished Verilog frontend.
name: sva_sva_notdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv:23: syntax error, unexpected '@'
name: asicworld_code_verilog_tutorial_tri_bufdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v:7)Generating RTLIL representation for module `\tri_buf'.Successfully finished Verilog frontend.
name: simple_muxtreedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v' to AST representation.Warning: Found one of those horrible `(synopsys|synthesis) full_case' comments.Yosys does support them but it is recommended to use Verilog `full_case' attributes instead!Warning: Found one of those horrible `(synopsys|synthesis) parallel_case' comments.Yosys does support them but it is recommended to use Verilog `parallel_case' attributes instead!Generating RTLIL representation for module `\usb_tx_phy'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v:27 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Generating RTLIL representation for module `\default_cases'.Generating RTLIL representation for module `\select_leaves'.Successfully finished Verilog frontend.
name: simple_dff_different_stylesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v' to AST representation.Generating RTLIL representation for module `\dff'.Generating RTLIL representation for module `\dffa'.Generating RTLIL representation for module `\dffa1'.Generating RTLIL representation for module `\dffa2'.Generating RTLIL representation for module `\dffa3'.Generating RTLIL representation for module `\dffa4'.Generating RTLIL representation for module `\dffsr1'.Generating RTLIL representation for module `\dffsr2'.Generating RTLIL representation for module `\dffsr2_sub'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_wire_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_wire_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_wire_example.v' to AST representation.Generating RTLIL representation for module `\wire_example'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_paritydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parity.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parity.v' to AST representation.Generating RTLIL representation for module `\parity'.Successfully finished Verilog frontend.
name: simple_aes_kexp128description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/aes_kexp128.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/aes_kexp128.v' to AST representation.Generating RTLIL representation for module `\aes_key_expand_128'.Successfully finished Verilog frontend.
name: simple_subbytesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v' to AST representation.Generating RTLIL representation for module `\subbytes_00'.Warning: Replacing memory \data_reg_var with list of registers. See /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:73, /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:54Warning: Replacing memory \data_array with list of registers. See /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:60, /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:49Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v:45 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: simple_fiedler-cooleydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v' to AST representation.Generating RTLIL representation for module `\up3down5'.Successfully finished Verilog frontend.
name: simple_omsp_dbg_uartdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/omsp_dbg_uart.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/omsp_dbg_uart.v' to AST representation.Generating RTLIL representation for module `\omsp_dbg_uart'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/omsp_dbg_uart.v:18 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: memories_shared_portsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/shared_ports.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/shared_ports.v' to AST representation.Generating RTLIL representation for module `\test'.Successfully finished Verilog frontend.
name: svinterfaces_svinterface1description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv:31: syntax error, unexpected TOK_ID
name: simple_constmuldivmoddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v' to AST representation.Generating RTLIL representation for module `\constmuldivmod'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_d_ff_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v' to AST representation.Generating RTLIL representation for module `\d_ff_gates'.Successfully finished Verilog frontend.
name: sva_basic00description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv:9: syntax error, unexpected ':', expecting TOK_ID or '#'
name: asicworld_code_verilog_tutorial_task_globaldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_task_global.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_task_global.v' to AST representation.Generating RTLIL representation for module `\task_global'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_good_codedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v' to AST representation.Generating RTLIL representation for module `\addbit'.Successfully finished Verilog frontend.
name: simple_arraycellsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arraycells.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arraycells.v' to AST representation.Generating RTLIL representation for module `\array_test001'.Generating RTLIL representation for module `\aoi12'.Successfully finished Verilog frontend.
name: errors_syntax_err09description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v' to AST representation.Generating RTLIL representation for module `\a'.Successfully finished Verilog frontend.
name: simple_multiplierdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v' to AST representation.Generating RTLIL representation for module `\Multiplier_flat'.Generating RTLIL representation for module `\Multiplier_2D'.Generating RTLIL representation for module `\RippleCarryAdder'.Generating RTLIL representation for module `\FullAdder'.Successfully finished Verilog frontend.
name: simple_usb_phy_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v' to AST representation.Generating RTLIL representation for module `\usb_phy_test01'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_fsm_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v' to AST representation.Generating RTLIL representation for module `\fsm_using_function'.Successfully finished Verilog frontend.
name: simple_attrib06_operator_suffixdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib06_operator_suffix.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib06_operator_suffix.v' to AST representation.Generating RTLIL representation for module `\bar'.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_reg_seq_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_seq_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_seq_example.v' to AST representation.Generating RTLIL representation for module `\reg_seq_example'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_d_latch_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v' to AST representation.Generating RTLIL representation for module `\d_latch_gates'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_first_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter.v' to AST representation.Generating RTLIL representation for module `\first_counter'.Successfully finished Verilog frontend.
name: errors_syntax_err12description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err12.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err12.v:1: syntax error, unexpected TOK_ID
name: asicworld_code_hdl_models_serial_crcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_serial_crc.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_serial_crc.v' to AST representation.Generating RTLIL representation for module `\serial_crc_ccitt'.Successfully finished Verilog frontend.
name: memories_amber23_sram_byte_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/amber23_sram_byte_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/amber23_sram_byte_en.v' to AST representation.Generating RTLIL representation for module `\generic_sram_byte_en'.Successfully finished Verilog frontend.
name: simple_signedexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v' to AST representation.Generating RTLIL representation for module `\signed_test01'.Successfully finished Verilog frontend.
name: errors_syntax_err02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err02.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err02.v:3: Syntax error.
name: asicworld_code_tidbits_reg_combo_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_combo_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_combo_example.v' to AST representation.Generating RTLIL representation for module `\reg_combo_example'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_combo_example.v:8 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: simple_forloopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v' to AST representation.Generating RTLIL representation for module `\forloops01'.Generating RTLIL representation for module `\forloops02'.Successfully finished Verilog frontend.
name: simple_attrib08_mod_instdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib08_mod_inst.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib08_mod_inst.v' to AST representation.Generating RTLIL representation for module `\bar'.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: errors_syntax_err13description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err13.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err13.v:1: syntax error
name: sva_extnetsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv' to AST representation.Generating RTLIL representation for module `\top'.Warning: Identifier `\A.i' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:4.Warning: Identifier `\B.o' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:5.Generating RTLIL representation for module `\A'.Warning: Identifier `\B.x' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:14.Warning: Identifier `\B.y' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:16.Generating RTLIL representation for module `\B'.Warning: Identifier `\A.y' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv:21.Successfully finished Verilog frontend.
name: simple_mem2regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v' to AST representation.Generating RTLIL representation for module `\mem2reg_test1'.Warning: Replacing memory \array with list of registers. See /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:15, /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:11Generating RTLIL representation for module `\mem2reg_test2'.Generating RTLIL representation for module `\mem2reg_test3'.Generating RTLIL representation for module `\mem2reg_test4'.Generating RTLIL representation for module `\mem2reg_test5'.Generating RTLIL representation for module `\mem2reg_test6'.Warning: Replacing memory \dout_array with list of registers. See /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:111, /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:108Warning: Replacing memory \din_array with list of registers. See /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:108, /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v:105Successfully finished Verilog frontend.
name: sva_basic05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv:13: syntax error, unexpected ':', expecting TOK_ID or '#'
name: asicworld_code_tidbits_fsm_using_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v' to AST representation.Generating RTLIL representation for module `\fsm_using_always'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v:29 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: sva_basic02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv:12: syntax error, unexpected ':', expecting TOK_ID or '#'
name: asicworld_code_hdl_models_clk_div_45description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div_45.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div_45.v' to AST representation.Generating RTLIL representation for module `\clk_div_45'.Successfully finished Verilog frontend.
name: simple_always01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always01.v' to AST representation.Generating RTLIL representation for module `\uut_always01'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_full_subtracter_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_subtracter_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_subtracter_gates.v' to AST representation.Generating RTLIL representation for module `\full_subtracter_gates'.Warning: Identifier `\borrows' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_subtracter_gates.v:18.Successfully finished Verilog frontend.
name: sva_basic04description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv:2: syntax error, unexpected ':', expecting TOK_ID or '#'
name: asicworld_code_hdl_models_parallel_crcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parallel_crc.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parallel_crc.v' to AST representation.Generating RTLIL representation for module `\parallel_crc_ccitt'.Successfully finished Verilog frontend.
name: errors_syntax_err08description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v:4: Syntax error.
name: simple_generatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Index in generate block prefix syntax at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v:110 is not constant!
name: asicworld_code_verilog_tutorial_if_elsedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_if_else.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_if_else.v' to AST representation.Generating RTLIL representation for module `\if_else'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_up_counter_loaddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter_load.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter_load.v' to AST representation.Generating RTLIL representation for module `\up_counter_load'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_full_adder_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_adder_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_adder_gates.v' to AST representation.Generating RTLIL representation for module `\full_adder_gates'.Successfully finished Verilog frontend.
name: simple_fsmdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fsm.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fsm.v' to AST representation.Generating RTLIL representation for module `\fsm_test'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_which_clockdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_which_clock.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_which_clock.v' to AST representation.Generating RTLIL representation for module `\which_clock'.Successfully finished Verilog frontend.
name: sva_basic03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv:7: syntax error, unexpected ':', expecting TOK_ID or '#'
name: asicworld_code_tidbits_blockingdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_blocking.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_blocking.v' to AST representation.Generating RTLIL representation for module `\blocking'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_addbitdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_addbit.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_addbit.v' to AST representation.Generating RTLIL representation for module `\addbit'.Successfully finished Verilog frontend.
name: simple_localparam_attrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/localparam_attr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/localparam_attr.v:4: syntax error, unexpected TOK_LOCALPARAM
name: asicworld_code_verilog_tutorial_parallel_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parallel_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parallel_if.v' to AST representation.Generating RTLIL representation for module `\parallel_if'.Successfully finished Verilog frontend.
name: simple_constpowerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v' to AST representation.Generating RTLIL representation for module `\constpower'.Successfully finished Verilog frontend.
name: simple_attrib04_net_vardescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib04_net_var.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib04_net_var.v' to AST representation.Generating RTLIL representation for module `\bar'.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_up_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter.v' to AST representation.Generating RTLIL representation for module `\up_counter'.Successfully finished Verilog frontend.
name: simple_operatorsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/operators.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/operators.v' to AST representation.Generating RTLIL representation for module `\optest'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_always_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_always_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_always_example.v' to AST representation.Generating RTLIL representation for module `\always_example'.Successfully finished Verilog frontend.
name: sva_basic01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv:10: syntax error, unexpected ':', expecting TOK_ID or '#'
name: sva_sva_throughoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv:5: syntax error, unexpected TOK_DEFAULT
name: sva_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv:11: syntax error, unexpected TOK_DEFAULT
name: asicworld_code_verilog_tutorial_d_ffdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_d_ff.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_d_ff.v' to AST representation.Generating RTLIL representation for module `\d_ff'.Successfully finished Verilog frontend.
name: simple_wreducedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v' to AST representation.Generating RTLIL representation for module `\wreduce_test0'.Generating RTLIL representation for module `\wreduce_test1'.Successfully finished Verilog frontend.
name: simple_task_funcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v' to AST representation.Generating RTLIL representation for module `\task_func_test01'.Generating RTLIL representation for module `\task_func_test02'.Generating RTLIL representation for module `\task_func_test03'.Generating RTLIL representation for module `\task_func_test04'.Generating RTLIL representation for module `\task_func_test05'.Successfully finished Verilog frontend.
name: simple_attrib01_moduledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib01_module.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib01_module.v' to AST representation.Generating RTLIL representation for module `\bar'.Generating RTLIL representation for module `\foo'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_decoder_2to4_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_2to4_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_2to4_gates.v' to AST representation.Generating RTLIL representation for module `\decoder_2to4_gates'.Successfully finished Verilog frontend.
name: simple_param_attrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/param_attr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/param_attr.v:4: syntax error, unexpected TOK_PARAMETER
name: memories_issue00335description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v' to AST representation.Generating RTLIL representation for module `\ram2'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_explicitdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_explicit.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_explicit.v' to AST representation.Generating RTLIL representation for module `\explicit'.Generating RTLIL representation for module `\dff'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_fsm_fulldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v' to AST representation.Generating RTLIL representation for module `\fsm_full'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v:39 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_mux_21description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v' to AST representation.Generating RTLIL representation for module `\mux_21'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_v2k_regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v' to AST representation.Generating RTLIL representation for module `\v2k_reg'.Successfully finished Verilog frontend.
name: sva_sva_rangedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv:5: syntax error, unexpected TOK_DEFAULT
name: asicworld_code_hdl_models_up_down_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_down_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_down_counter.v' to AST representation.Generating RTLIL representation for module `\up_down_counter'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_commentdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v' to AST representation.Generating RTLIL representation for module `\addbit'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_half_adder_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_half_adder_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_half_adder_gates.v' to AST representation.Generating RTLIL representation for module `\half_adder_gates'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_GrayCounterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_GrayCounter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_GrayCounter.v' to AST representation.Generating RTLIL representation for module `\GrayCounter'.Successfully finished Verilog frontend.
name: simple_scopesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v' to AST representation.Generating RTLIL representation for module `\scopes_test_01'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_asyn_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_asyn_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_asyn_reset.v' to AST representation.Generating RTLIL representation for module `\asyn_reset'.Successfully finished Verilog frontend.
name: simple_paramodsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v' to AST representation.Generating RTLIL representation for module `\pm_test1'.Generating RTLIL representation for module `\pm_test2'.Generating RTLIL representation for module `\pm_test3'.Generating RTLIL representation for module `\inc'.Successfully finished Verilog frontend.
name: simple_hierarchydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v' to AST representation.Generating RTLIL representation for module `\top'.Generating RTLIL representation for module `\submod'.Successfully finished Verilog frontend.
name: memories_firrtl_938description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/firrtl_938.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/firrtl_938.v' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: errors_syntax_err07description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err07.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err07.v:4: Syntax error.
name: simple_arrays01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arrays01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arrays01.v' to AST representation.Generating RTLIL representation for module `\uut_arrays01'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_pri_encoder_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v' to AST representation.Generating RTLIL representation for module `\pri_encoder_using_assign'.Successfully finished Verilog frontend.
name: errors_syntax_err06description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v:4: Syntax error.
name: asicworld_code_verilog_tutorial_multiplydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v' to AST representation.Generating RTLIL representation for module `\muliply'.Successfully finished Verilog frontend.
name: simple_specifydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/specify.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/specify.v:3: syntax error, unexpected '=', expecting '(' or '['
name: simple_undef_eqx_nexdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/undef_eqx_nex.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/undef_eqx_nex.v' to AST representation.Generating RTLIL representation for module `\undef_eqx_nex'.Successfully finished Verilog frontend.
name: simple_loopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/loops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/loops.v' to AST representation.Generating RTLIL representation for module `\aes'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v:30: syntax error, unexpected ';', expecting '(' or '['
name: asicworld_code_verilog_tutorial_simple_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v' to AST representation.Generating RTLIL representation for module `\simple_if'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v:6 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: errors_syntax_err04description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v:2: Syntax error.
name: errors_syntax_err10description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v:2: Syntax error.
name: simple_retimedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/retime.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/retime.v' to AST representation.Generating RTLIL representation for module `\retime_test'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_dff_async_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_async_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_async_reset.v' to AST representation.Generating RTLIL representation for module `\dff_async_reset'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_n_out_primitivedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v' to AST representation.Generating RTLIL representation for module `\n_out_primitive'.Successfully finished Verilog frontend.
name: memories_no_implicit_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/no_implicit_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/no_implicit_en.v' to AST representation.Generating RTLIL representation for module `\test'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_decoder_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_case.v' to AST representation.Generating RTLIL representation for module `\decoder_using_case'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_case.v:18 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: simple_always03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always03.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always03.v' to AST representation.Generating RTLIL representation for module `\uut_always03'.Successfully finished Verilog frontend.
name: asicworld_code_tidbits_fsm_using_single_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v' to AST representation.Generating RTLIL representation for module `\fsm_using_single_always'.Successfully finished Verilog frontend.
name: simple_i2c_master_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v' to AST representation.Generating RTLIL representation for module `\i2c_test01'.Generating RTLIL representation for module `\i2c_test02'.Successfully finished Verilog frontend.
name: errors_syntax_err01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v:2: Syntax error.
name: asicworld_code_tidbits_syn_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_syn_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_syn_reset.v' to AST representation.Generating RTLIL representation for module `\syn_reset'.Successfully finished Verilog frontend.
name: errors_syntax_err03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err03.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err03.v:3: Syntax error.
name: simple_graphtestdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/graphtest.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/graphtest.v' to AST representation.Generating RTLIL representation for module `\graphtest'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_one_hot_cntdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_one_hot_cnt.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_one_hot_cnt.v' to AST representation.Generating RTLIL representation for module `\one_hot_cnt'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_tff_async_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_async_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_async_reset.v' to AST representation.Generating RTLIL representation for module `\tff_async_reset'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_gray_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_gray_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_gray_counter.v' to AST representation.Generating RTLIL representation for module `\gray_counter'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_parity_using_bitwisedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_bitwise.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_bitwise.v' to AST representation.Generating RTLIL representation for module `\parity_using_bitwise'.Successfully finished Verilog frontend.
name: asicworld_code_hdl_models_encoder_4to2_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_4to2_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_4to2_gates.v' to AST representation.Generating RTLIL representation for module `\encoder_4to2_gates'.Successfully finished Verilog frontend.
name: simple_memorydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v:39: syntax error, unexpected ','
name: asicworld_code_hdl_models_tff_sync_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_sync_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_sync_reset.v' to AST representation.Generating RTLIL representation for module `\tff_sync_reset'.Successfully finished Verilog frontend.
name: errors_syntax_err11description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err11.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err11.v:2: Syntax error.
name: asicworld_code_verilog_tutorial_escape_iddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_escape_id.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_escape_id.v' to AST representation.Generating RTLIL representation for module `\1dff'.Successfully finished Verilog frontend.
name: asicworld_code_verilog_tutorial_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter.v' to AST representation.Generating RTLIL representation for module `\counter'.Successfully finished Verilog frontend.
name: simple_sincosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/sincos.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/sincos.v' to AST representation.Generating RTLIL representation for module `\d'.Successfully finished Verilog frontend.
name: simple_realexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v' to AST representation.Generating RTLIL representation for module `\demo_001'.Warning: converting real value 1.234500e+02 to binary 8'01111011 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:4.Warning: converting real value 1.232000e+02 to binary 123 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:9.Warning: converting real value 1.236500e+02 to binary 124 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:10.Warning: converting real value 1.232000e+02 to binary 123 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:11.Warning: converting real value 1.236500e+02 to binary 124 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:12.Generating RTLIL representation for module `\demo_002'.Warning: converting real value 4.294967e+09 to binary 64'0000000000000000000000000000000011111111111111111111111111111111 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:19.Warning: converting real value -1.000000e+00 to binary 64'1111111111111111111111111111111111111111111111111111111111111111 at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:20.Generating RTLIL representation for module `\demo_003'.Generating RTLIL representation for module `\demo_004'.Warning: Replacing floating point parameter demo_real.$1 = 1.000000 with string at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v:31.Successfully finished Verilog frontend.
name: simple_forgen01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen01.v' to AST representation.Generating RTLIL representation for module `\uut_forgen01'.Successfully finished Verilog frontend.
name: simple_wandwordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v:3: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: asicworld_code_hdl_models_decoder_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_assign.v' to AST representation.Generating RTLIL representation for module `\decoder_using_assign'.Successfully finished Verilog frontend.
name: simple_hierdefparamdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v:7: syntax error, unexpected '[', expecting TOK_PACKAGESEP or '=' or '.'
name: hana_test_parserdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::4 error in parsing: (syntax error, unexpected vENDMODULE)ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::11 Odin does not handle inouts (io)but WITHOUT ANY WARRANTY; without even the implied warranty ofAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::652
name: hana_test_simulation_shifterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_seqdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_incdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_techmap_techdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_sopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_xnordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_intermoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_xordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_bufferdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_parse2synthtransdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::7 Odin does not handle signed regs (a)the Free Software Foundation; either version 3 of the License, orAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessSymbolListWith::792
name: hana_test_simulation_nanddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_anddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_nordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_techmapdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_vlibdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: hana_test_simulation_ordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1097 Unsuported tokenmodule VCC (output supply1 out); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1098 error in parsing: (syntax error, unexpected vENDMODULE)endmodulePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v::1100 Unsuported tokenmodule GND (output supply0 out); ^~~~ERROR (5)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: asicworld_code_verilog_tutorial_decoder_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v::18 You've defined this driver decoder_always^out~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_hdl_models_lfsr_updowndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr_updown.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr_updown.v::29 error in parsing: (syntax error, unexpected vNUMBER) count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: errors_syntax_err05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v::2 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')input x[2:0];
name: simple_attrib09_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v::8 error in parsing: (syntax error, unexpected '(') (* full_case, parallel_case *)ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v::19 Module already has input with this name clk input wire clk;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::514
name: asicworld_code_hdl_models_encoder_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v::56 You've defined this driver encoder_using_if^binary_out~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_verilog_tutorial_bus_condescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_bus_con.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_bus_con.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: bus_con==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_uartdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_uart.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurAssertion failed(rnode[1] && rnode[1]->type == NUMBERS)@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_util.cpp]get_name_of_pins::711
name: asicworld_code_hdl_models_mux_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_case.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: mux_using_case==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_verilog_tutorial_fsm_full_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full_tb.v::10 outfile define cannot be found file = $fopen(`outfile);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: memories_read_two_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/read_two_mux.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/read_two_mux.v::8 error in parsing: (syntax error, unexpected '(')(* keep *) reg dummy;ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/read_two_mux.v::7 Odin doesn't support arrays declared [m:n] where m is less than n.reg [7:0] bram[0:255];Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]define_nets_with_driver::1299
name: simple_carryadddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v::16 error in parsing: (syntax error, unexpected '.') assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/carryadd.v::19 error in parsing: (syntax error, unexpected vEND) endERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_valuesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v::5 Odin does not handle signed ports (d)input signed [3:0] d;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: simple_forgen02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: memories_simple_sram_byte_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/simple_sram_byte_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/simple_sram_byte_en.v::22 error in parsing: (syntax error, unexpected vPLUS_COLON) mem[i_address][i*8 +: 8] <= i_write_data[i*8 +: 8];ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_attrib02_port_decldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v::2 error in parsing: (syntax error, unexpected '(') (* this_is_clock = 1 *)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v::7 error in parsing: (syntax error, unexpected '(') (* an_output_register = 1*)ERROR (4)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib02_port_decl.v::1 No matching declaration for port clkAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]resolve_ports::407
name: asicworld_code_hdl_models_arbiter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v::15 error in parsing: (syntax error, unexpected vDELAY_ID)always #1 clk = ~clk;ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter_tb.v::22 outfile define cannot be found file = $fopen(`outfile);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: simple_processdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/process.v::34 error in parsing: (syntax error, unexpected ',') 2'b01, 2'b10:ERROR (3)::NETLIST_ERROR Found multiple top level modules blocking_cond uutAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: asicworld_code_verilog_tutorial_first_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter_tb.v::9 outfile define cannot be found file = $fopen(`outfile);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: simple_always02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always02.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always02.v::11 You've defined the driver "count~0" twiceendAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_registered_assignment::3662
name: memories_issue00710description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00710.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00710.v::8 error in parsing: (syntax error, unexpected '(')(* keep *) reg dummy;ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00710.v::12 Missing declaration of this symbol dummy dummy <= 1'b0;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_util.cpp]get_size_of_variable::884
name: asicworld_code_hdl_models_arbiterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_arbiter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: arbiter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_rotatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v::14 error in parsing: (syntax error, unexpected vFOR, expecting vENDGENERATE) for (i = 0; i < 5; i = i + 1)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v::24 error in parsing: (syntax error, unexpected vEND) endPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v::30 error in parsing: (syntax error, unexpected '.', expecting '=') assign netgen[i-1].in = netgen[i].out;ERROR (5)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/rotate.v::18 Missing declaration of this symbol j for (j = 0; j < 32; j = j + 1)Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_elaborate.cpp]verify_genvars::2690
name: asicworld_code_tidbits_nonblockingdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_nonblocking.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_nonblocking.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: nonblocking==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_dff_initdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v::13 error in parsing: (syntax error, unexpected '(') (* init = 32'd1 *)ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_init.v::11 No matching declaration for port n1module dff1_test(n1, n1_inv, clk);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]resolve_ports::407
name: simple_attrib03_parameterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib03_parameter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib03_parameter.v::3 error in parsing: (syntax error, unexpected '(') (* bus_width *)ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib03_parameter.v::26 Can't find parameter name WIDTH in module bar bar # (.WIDTH(8)) bar_instance (clk, rst, inp, out);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_elaborate.cpp]update_instance_parameter_table::2448
name: asicworld_code_verilog_tutorial_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: decoder==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_mem_arstdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem_arst.v::5 error in parsing: (syntax error, unexpected '(') (* gentb_constant = 1 *)ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_encoder_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_case.v::40 You've defined this driver encoder_using_case^binary_out~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: simple_vloghammerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v::12 Odin does not handle signed ports (a) input signed [3:0] a;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: asicworld_code_verilog_tutorial_simple_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: svinterfaces_svinterface_at_topdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv::4 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') input logic clk,ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_mux_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: mux_using_if==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_mux_2to1_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: mux_2to1_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_parity_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR This function port data_in[0] is unused in module parityWARNING (3)::NETLIST_ERROR This function port data_in[1] is unused in module parityWARNING (4)::NETLIST_ERROR This function port data_in[2] is unused in module parityWARNING (5)::NETLIST_ERROR This function port data_in[3] is unused in module parityWARNING (6)::NETLIST_ERROR This function port data_in[4] is unused in module parityWARNING (7)::NETLIST_ERROR This function port data_in[5] is unused in module parityWARNING (8)::NETLIST_ERROR This function port data_in[6] is unused in module parityWARNING (9)::NETLIST_ERROR This function port data_in[7] is unused in module parityWARNING (10)::NETLIST_ERROR This function port data_in[8] is unused in module parityWARNING (11)::NETLIST_ERROR This function port data_in[9] is unused in module parityWARNING (12)::NETLIST_ERROR This function port data_in[10] is unused in module parityWARNING (13)::NETLIST_ERROR This function port data_in[11] is unused in module parityWARNING (14)::NETLIST_ERROR This function port data_in[12] is unused in module parityWARNING (15)::NETLIST_ERROR This function port data_in[13] is unused in module parityWARNING (16)::NETLIST_ERROR This function port data_in[14] is unused in module parityWARNING (17)::NETLIST_ERROR This function port data_in[15] is unused in module parityWARNING (18)::NETLIST_ERROR This function port data_in[16] is unused in module parityWARNING (19)::NETLIST_ERROR This function port data_in[17] is unused in module parityWARNING (20)::NETLIST_ERROR This function port data_in[18] is unused in module parityWARNING (21)::NETLIST_ERROR This function port data_in[19] is unused in module parityWARNING (22)::NETLIST_ERROR This function port data_in[20] is unused in module parityWARNING (23)::NETLIST_ERROR This function port data_in[21] is unused in module parityWARNING (24)::NETLIST_ERROR This function port data_in[22] is unused in module parityWARNING (25)::NETLIST_ERROR This function port data_in[23] is unused in module parityWARNING (26)::NETLIST_ERROR This function port data_in[24] is unused in module parityWARNING (27)::NETLIST_ERROR This function port data_in[25] is unused in module parityWARNING (28)::NETLIST_ERROR This function port data_in[26] is unused in module parityWARNING (29)::NETLIST_ERROR This function port data_in[27] is unused in module parityWARNING (30)::NETLIST_ERROR This function port data_in[28] is unused in module parityWARNING (31)::NETLIST_ERROR This function port data_in[29] is unused in module parityWARNING (32)::NETLIST_ERROR This function port data_in[30] is unused in module parityWARNING (33)::NETLIST_ERROR This function port data_in[31] is unused in module parity--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_function.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: parity_using_function==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.0ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_camdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_cam.v::47 You've defined this driver cam^cam_addr_combo~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_verilog_tutorial_flip_flopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_flip_flop.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_flip_flop.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: flif_flop==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_clk_divdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: clk_div==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_specman_switch_fabricdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::22 error in parsing: (syntax error, unexpected '(')(* gentb_clock *)WARNING (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~0) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (4)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~1) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (5)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~2) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (6)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~3) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (7)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~4) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (8)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~5) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (9)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~6) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (10)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack3~7) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (11)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~0) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (12)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~1) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (13)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~2) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (14)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~3) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (15)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~4) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (16)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~5) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (17)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~6) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (18)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack4~7) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (19)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~0) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (20)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~1) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (21)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~2) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (22)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~3) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (23)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~4) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (24)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~5) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (25)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~6) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (26)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v::20 This output is undriven (switch_fabric^data_out_ack5~7) and will be removedoutput [7:0] data_out_ack3, data_out_ack4, data_out_ack5;WARNING (27)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~106 is itself undriven.WARNING (28)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~107 is itself undriven.WARNING (29)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~108 is itself undriven.WARNING (30)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~109 is itself undriven.WARNING (31)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~110 is itself undriven.WARNING (32)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~111 is itself undriven.WARNING (33)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~112 is itself undriven.WARNING (34)::NETLIST_ERROR Net (null) driving node switch_fabric.port_3^nMUX~14^MUX_2~113 is itself undriven.WARNING (35)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~115 is itself undriven.WARNING (36)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~116 is itself undriven.WARNING (37)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~117 is itself undriven.WARNING (38)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~118 is itself undriven.WARNING (39)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~119 is itself undriven.WARNING (40)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~120 is itself undriven.WARNING (41)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~121 is itself undriven.WARNING (42)::NETLIST_ERROR Net (null) driving node switch_fabric.port_4^nMUX~18^MUX_2~122 is itself undriven.WARNING (43)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~124 is itself undriven.WARNING (44)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~125 is itself undriven.WARNING (45)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~126 is itself undriven.WARNING (46)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~127 is itself undriven.WARNING (47)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~128 is itself undriven.WARNING (48)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~129 is itself undriven.WARNING (49)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~130 is itself undriven.WARNING (50)::NETLIST_ERROR Net (null) driving node switch_fabric.port_5^nMUX~22^MUX_2~131 is itself undriven.WARNING (51)::NETLIST_ERROR Net switch_fabric^data_out_ack3~0 driving node switch_fabric^data_out_ack3~0 is itself undriven.WARNING (52)::NETLIST_ERROR Net switch_fabric^data_out_ack3~1 driving node switch_fabric^data_out_ack3~1 is itself undriven.WARNING (53)::NETLIST_ERROR Net switch_fabric^data_out_ack3~2 driving node switch_fabric^data_out_ack3~2 is itself undriven.WARNING (54)::NETLIST_ERROR Net switch_fabric^data_out_ack3~3 driving node switch_fabric^data_out_ack3~3 is itself undriven.WARNING (55)::NETLIST_ERROR Net switch_fabric^data_out_ack3~4 driving node switch_fabric^data_out_ack3~4 is itself undriven.WARNING (56)::NETLIST_ERROR Net switch_fabric^data_out_ack3~5 driving node switch_fabric^data_out_ack3~5 is itself undriven.WARNING (57)::NETLIST_ERROR Net switch_fabric^data_out_ack3~6 driving node switch_fabric^data_out_ack3~6 is itself undriven.WARNING (58)::NETLIST_ERROR Net switch_fabric^data_out_ack3~7 driving node switch_fabric^data_out_ack3~7 is itself undriven.WARNING (59)::NETLIST_ERROR Net switch_fabric^data_out_ack4~0 driving node switch_fabric^data_out_ack4~0 is itself undriven.WARNING (60)::NETLIST_ERROR Net switch_fabric^data_out_ack4~1 driving node switch_fabric^data_out_ack4~1 is itself undriven.WARNING (61)::NETLIST_ERROR Net switch_fabric^data_out_ack4~2 driving node switch_fabric^data_out_ack4~2 is itself undriven.WARNING (62)::NETLIST_ERROR Net switch_fabric^data_out_ack4~3 driving node switch_fabric^data_out_ack4~3 is itself undriven.WARNING (63)::NETLIST_ERROR Net switch_fabric^data_out_ack4~4 driving node switch_fabric^data_out_ack4~4 is itself undriven.WARNING (64)::NETLIST_ERROR Net switch_fabric^data_out_ack4~5 driving node switch_fabric^data_out_ack4~5 is itself undriven.WARNING (65)::NETLIST_ERROR Net switch_fabric^data_out_ack4~6 driving node switch_fabric^data_out_ack4~6 is itself undriven.WARNING (66)::NETLIST_ERROR Net switch_fabric^data_out_ack4~7 driving node switch_fabric^data_out_ack4~7 is itself undriven.WARNING (67)::NETLIST_ERROR Net switch_fabric^data_out_ack5~0 driving node switch_fabric^data_out_ack5~0 is itself undriven.WARNING (68)::NETLIST_ERROR Net switch_fabric^data_out_ack5~1 driving node switch_fabric^data_out_ack5~1 is itself undriven.WARNING (69)::NETLIST_ERROR Net switch_fabric^data_out_ack5~2 driving node switch_fabric^data_out_ack5~2 is itself undriven.WARNING (70)::NETLIST_ERROR Net switch_fabric^data_out_ack5~3 driving node switch_fabric^data_out_ack5~3 is itself undriven.WARNING (71)::NETLIST_ERROR Net switch_fabric^data_out_ack5~4 driving node switch_fabric^data_out_ack5~4 is itself undriven.WARNING (72)::NETLIST_ERROR Net switch_fabric^data_out_ack5~5 driving node switch_fabric^data_out_ack5~5 is itself undriven.WARNING (73)::NETLIST_ERROR Net switch_fabric^data_out_ack5~6 driving node switch_fabric^data_out_ack5~6 is itself undriven.WARNING (74)::NETLIST_ERROR Net switch_fabric^data_out_ack5~7 driving node switch_fabric^data_out_ack5~7 is itself undriven.--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: switch_fabric==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 10.0ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.01 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_parity_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_assign.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: parity_using_assign==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_lfsrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_lfsr.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: lfsr==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 2.0ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_dff_sync_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_sync_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_sync_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: dff_sync_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: memories_implicit_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/implicit_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/implicit_en.v::17 error in parsing: (syntax error, unexpected ':') mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[wr_addr][ 7: 0];ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_rom_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_rom_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_rom_using_case.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: rom_using_case==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 4.3ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_mux_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_assign.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: mux_using_assign==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_repwhiledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/repwhile.v::10 While statements are NOT supported endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]newWhile::1193
name: simple_macrosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v::57 A is redefined, overwritting its value `define AWARNING (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v::94 A is redefined, overwritting its value `define AWARNING (4)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v::160 A is redefined, overwritting its value `define AWARNING (5)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v::197 A is redefined, overwritting its value `define APARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/macros.v::243 error in parsing: (syntax error, unexpected vNUMBER, expecting ';' or ',')assign dout_a = din_a | `SIZE'ha;ERROR (7)::NETLIST_ERROR Found multiple top level modules test_def test_ifdef test_comment_in_macroAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_partseldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/partsel.v::2 Could not resolve initial assignment to a constant value, skippingwire [5:0] offset = idx << 2;ERROR (3)::NETLIST_ERROR Found multiple top level modules partsel_test001 partsel_test002Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: sva_sva_notdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv::9 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or vSIGNED or '[') localparam integer maxdelay = 8;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv::23 error in parsing: (syntax error, unexpected '@') @(posedge clk)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv::24 Unsuported token disable iff (reset) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_not.sv::30 error in parsing: (syntax error, unexpected '@') @(posedge clk)ERROR (7)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: asicworld_code_verilog_tutorial_tri_bufdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_tri_buf.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: tri_buf==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_muxtreedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/muxtree.v::63 error in parsing: (syntax error, unexpected ',') 3'b000, 3'b111: y <= 0;ERROR (3)::NETLIST_ERROR Found multiple top level modules usb_tx_phy default_casesAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_dff_different_stylesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v::86 error in parsing: (syntax error, unexpected '(')(* gentb_clock *)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/dff_different_styles.v::91 error in parsing: (syntax error, unexpected '(', expecting $end)(* gentb_skip *)ERROR (4)::NETLIST_ERROR Found multiple top level modules dff dffa dffa1 dffa2 dffa3 dffa4 dffsr1 dffsr2Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: asicworld_code_tidbits_wire_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_wire_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_wire_example.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: wire_example==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: asicworld_code_verilog_tutorial_paritydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parity.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parity.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: parity==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_aes_kexp128description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/aes_kexp128.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurAssertion failed(false)@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_util.cpp]get_name_of_pins::779
name: simple_subbytesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v::49 indexing into memory with subbytes_00 has larger input than memory. Unused pins: subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ data_array[0] = data_i_var[ 31: 24];WARNING (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/subbytes.v::50 indexing into memory with subbytes_00 has larger input than memory. Unused pins: subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ subbytes_00^ZGZ data_array[1] = data_i_var[ 23: 16];ERROR (4)::NETLIST_ERROR Attempted to reassign input port addr2 to memory subbytes_00.data_array.Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/memories.cpp]add_input_port_to_memory::177
name: simple_fiedler-cooleydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') cnt_dn = count_out - 3'b 101;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fiedler-cooley.v::20 error in parsing: (syntax error, unexpected vSYMBOL_ID) 2'b 00 : count_nxt = data_in;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_omsp_dbg_uartdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/omsp_dbg_uart.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/omsp_dbg_uart.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: omsp_dbg_uart==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: memories_shared_portsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/shared_ports.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/shared_ports.v::17 error in parsing: (syntax error, unexpected ':') mem[wr_addr1][15:0] <= wr_data;ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_implicit_portsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/implicit_ports.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/implicit_ports.v::11 error in parsing: (syntax error, unexpected ',', expecting '(') .b, // Implicit connection is equivalent to .b(b)ERROR (3)::NETLIST_ERROR Found multiple top level modules alu named_portsAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: svinterfaces_svinterface1description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv::4 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') input logic clk,ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_constmuldivmoddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v::4 Divide operation not supported by Odin 0: Y = A / 8'd0;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]create_operation_node::4114
name: asicworld_code_hdl_models_d_ff_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_ff_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: d_ff_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.8ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: sva_basic00description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv::9 error in parsing: (syntax error, unexpected ':', expecting vSYMBOL_ID or '#') test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |=> consequent )PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic00.sv::9 Unsuported token test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |=> consequent ) ^~~~ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: asicworld_code_verilog_tutorial_task_globaldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_task_global.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: asicworld_code_verilog_tutorial_good_codedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v::10 This output is undriven (addbit^sum) and will be removed output sum;WARNING (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v::11 This output is undriven (addbit^co) and will be removed output co;WARNING (4)::NETLIST_ERROR Net addbit^sum driving node addbit^sum is itself undriven.WARNING (5)::NETLIST_ERROR Net addbit^co driving node addbit^co is itself undriven.--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_good_code.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: addbit==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_arraycellsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arraycells.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arraycells.v::7 error in parsing: (syntax error, unexpected '[', expecting '(') aoi12 p [31:0] (a, b, c, y);ERROR (3)::NETLIST_ERROR Found multiple top level modules array_test001 aoi12Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: errors_syntax_err09description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err09.v::1 Ports of type net cannot be initializedAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::570
name: simple_multiplierdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/multiplier.v::40 no match for parameter MSBwire [MSB:0] PP;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]resolve_symbol_node::307
name: simple_usb_phy_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/usb_phy_tests.v::33 You've defined this driver usb_phy_test01^fs_ce twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks. endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_tidbits_fsm_using_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurAssertion failed(node_min->type == NUMBERS && node_max->type == NUMBERS)@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]define_nets_with_driver::1215
name: simple_attrib06_operator_suffixdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib06_operator_suffix.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib06_operator_suffix.v::10 error in parsing: (syntax error, unexpected '*') else out <= inp_a + (* ripple_adder *) inp_b;ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib06_operator_suffix.v::21 This module port foo.bar_instance^clk is unused in module bar bar bar_instance (clk, rst, inp_a, inp_b, out);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]connect_module_instantiation_and_alias::2173
name: asicworld_code_tidbits_reg_seq_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_seq_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_seq_example.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: reg_seq_example==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: asicworld_code_hdl_models_d_latch_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_d_latch_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: d_latch_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_verilog_tutorial_first_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_first_counter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: first_counter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: errors_syntax_err12description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err12.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err12.v::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_serial_crcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_serial_crc.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_serial_crc.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: serial_crc_ccitt==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 5.2ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.01 seconds (max_rss 7.0 MiB)
name: memories_amber23_sram_byte_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/amber23_sram_byte_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/amber23_sram_byte_en.v::60 Odin doesn't support arrays declared [m:n] where m is less than n.reg [DATA_WIDTH-1:0] mem [0:2**ADDRESS_WIDTH-1];Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]define_nets_with_driver::1299
name: simple_signedexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/signedexpr.v::3 Odin does not handle signed ports (a)input signed [1:0] a;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: errors_syntax_err02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err02.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err02.v::3 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID) input integer [3:0]xERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_tidbits_reg_combo_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_combo_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_reg_combo_example.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: reg_combo_example==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_forloopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forloops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR Found multiple top level modules forloops01 forloops02Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_attrib08_mod_instdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib08_mod_inst.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib08_mod_inst.v::19 error in parsing: (syntax error, unexpected '(') (* my_module_instance = 99 *)ERROR (3)::NETLIST_ERROR Found multiple top level modules bar fooAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: errors_syntax_err13description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err13.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err13.v::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vPARAMETER or ')')ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: sva_extnetsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/extnets.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: simple_mem2regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v::28 error in parsing: (syntax error, unexpected '(')(* mem2reg *)ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/mem2reg.v::65 Odin does not handle signed ports (result1) output signed [9:0] result1;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: sva_basic05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic05.sv::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_tidbits_fsm_using_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_always.v::52 You've defined this driver fsm_using_always^next_state~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: sva_basic02description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic02.sv::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_clk_div_45description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div_45.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_clk_div_45.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: clk_div_45==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.2ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: simple_always01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always01.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: uut_always01==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.3ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_full_subtracter_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_subtracter_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_subtracter_gates.v::18 Missing declaration of this symbol borrowsxor U_diff (difference,borrow1,borrow2,borrows);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_util.cpp]get_name_of_pins::745
name: sva_basic04description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic04.sv::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_parallel_crcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parallel_crc.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR Net (null) driving node parallel_crc_ccitt^nMUX~20^MUX_2~64 is itself undriven.WARNING (3)::NETLIST_ERROR Net (null) driving node parallel_crc_ccitt^nMUX~20^MUX_2~65 is itself undriven.WARNING (4)::NETLIST_ERROR Net (null) driving node parallel_crc_ccitt^nMUX~20^MUX_2~66 is itself undriven.WARNING (5)::NETLIST_ERROR Net (null) driving node parallel_crc_ccitt^nMUX~20^MUX_2~67 is itself undriven.--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parallel_crc.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: parallel_crc_ccitt==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 8.9ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.01 seconds (max_rss 7.0 MiB)
name: errors_syntax_err08description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err08.v::4 error in parsing: (syntax error, unexpected vNUMBER, expecting ';' or ',')assign y = x 55;
name: simple_generatedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v::26 error in parsing: (syntax error, unexpected vFOR, expecting vENDGENERATE) for (i = 0; i < 8; i = i + 1) begin:gen3PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v::35 error in parsing: (syntax error, unexpected vEND) endERROR (4)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/generate.v::45 Module already has input with this name clkinput clk;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::514
name: asicworld_code_verilog_tutorial_if_elsedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_if_else.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: asicworld_code_hdl_models_up_counter_loaddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter_load.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter_load.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: up_counter_load==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_full_adder_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_adder_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_full_adder_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: full_adder_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_fsmdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fsm.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fsm.v::9 error in parsing: (syntax error, unexpected '(')(* gentb_constant = 0 *)ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/fsm.v::66 You've defined the driver "cnt~0" twiceendAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_registered_assignment::3662
name: asicworld_code_verilog_tutorial_which_clockdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_which_clock.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_which_clock.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: which_clock==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: sva_basic03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic03.sv::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_tidbits_blockingdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_blocking.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_blocking.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: blocking==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_verilog_tutorial_addbitdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_addbit.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_addbit.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: addbit==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: simple_localparam_attrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/localparam_attr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/localparam_attr.v::3 error in parsing: (syntax error, unexpected '(')(* LOCALPARAM_ATTRIBUTE = "attribute_content" *)Assertion failed(node_is_constant(var_node->children[1]) && node_is_constant(var_node->children[2]))@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_elaborate.cpp]reduce_expressions::2295
name: asicworld_code_verilog_tutorial_parallel_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_parallel_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: simple_constpowerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constpower.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: constpower==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 46.8ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.05 seconds (max_rss 7.5 MiB)
name: simple_attrib04_net_vardescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib04_net_var.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib04_net_var.v::7 error in parsing: (syntax error, unexpected '(') (* this_is_a_prescaler *)ERROR (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib04_net_var.v::14 Missing declaration of this symbol counter counter <= counter + 1;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_util.cpp]get_size_of_variable::884
name: asicworld_code_hdl_models_up_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_counter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: up_counter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.4ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_operatorsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/operators.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/operators.v::7 Odin does not handle signed ports (s1)input signed [3:0] s1, s2;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: asicworld_code_verilog_tutorial_always_exampledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_always_example.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: sva_basic01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/basic01.sv::1 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: sva_sva_throughoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv::5 error in parsing: (syntax error, unexpected vDEFAULT) default clocking @(posedge clk); endclockingPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') assert property (PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv::13 error in parsing: (syntax error, unexpected voPAL) a |=> b && cPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv::16 error in parsing: (syntax error, unexpected voPAL) b && c |=> b && d--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_throughout.sv to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: top==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: sva_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::11 error in parsing: (syntax error, unexpected vDEFAULT) default clocking @(posedge clk); endclockingPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::12 Unsuported token default disable iff (reset); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::14 error in parsing: (syntax error, unexpected voPAL) assert property (up |=> cnt == $past(cnt) + 8'd 1);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::15 error in parsing: (syntax error, unexpected '*') assert property (up [*2] |=> cnt == $past(cnt, 2) + 8'd 2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::16 error in parsing: (syntax error, unexpected '#', expecting ')' or ',') assert property (up ##1 up |=> cnt == $past(cnt, 2) + 8'd 2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::19 error in parsing: (syntax error, unexpected '>') assume property (down |-> !up);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::21 error in parsing: (syntax error, unexpected '#', expecting ')' or ',') assert property (up ##1 down |=> cnt == $past(cnt, 2));PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::22 error in parsing: (syntax error, unexpected voPAL) assert property (down |=> cnt == $past(cnt) - 8'd 1);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::25 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') down [*n] |=> cnt == $past(cnt, n) - n;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::28 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') assert property (down_n(8'd 3));PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/counter.sv::29 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') assert property (down_n(8'd 5));ERROR (14)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: asicworld_code_verilog_tutorial_d_ffdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_d_ff.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_d_ff.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: d_ff==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_wreducedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wreduce.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR Found multiple top level modules wreduce_test0 wreduce_test1Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_task_funcdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v::28 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') reset_w;ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/task_func.v::40 Module already has input with this name clkinput clk;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::514
name: simple_attrib01_moduledescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib01_module.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib01_module.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: foo==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_decoder_2to4_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_2to4_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_2to4_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: decoder_2to4_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_param_attrdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/param_attr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/param_attr.v::3 error in parsing: (syntax error, unexpected '(')(* PARAMETER_ATTRIBUTE = "attribute_content" *)Assertion failed(node_is_constant(var_node->children[1]) && node_is_constant(var_node->children[2]))@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_elaborate.cpp]reduce_expressions::2295
name: memories_issue00335description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/issue00335.v::13 Odin doesn't support arrays declared [m:n] where m is less than n. reg [63:0] mem [0:(1 << SIZE)-1];Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]define_nets_with_driver::1299
name: asicworld_code_verilog_tutorial_explicitdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_explicit.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: asicworld_code_verilog_tutorial_fsm_fulldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v::76 You've defined this driver fsm_full^next_state~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_verilog_tutorial_mux_21description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: mux_21==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_verilog_tutorial_v2k_regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v::10 Odin does not handle signed regs (data)reg signed [7:0] data = 8'shF0;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessSymbolListWith::792
name: sva_sva_rangedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv::5 error in parsing: (syntax error, unexpected vDEFAULT) default clocking @(posedge clk); endclockingPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') assert property (PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv::13 error in parsing: (syntax error, unexpected voPAL) b |=> ##5 dPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv::16 error in parsing: (syntax error, unexpected voPAL) b || (c && !d) |=> c--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/sva/sva_range.sv to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: top==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.8ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_up_down_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_down_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_up_down_counter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: up_down_counter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 2.1ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_verilog_tutorial_commentdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v::16 This output is undriven (addbit^sum) and will be removedoutput sum;WARNING (3)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v::17 This output is undriven (addbit^co) and will be removedoutput co;WARNING (4)::NETLIST_ERROR Net addbit^sum driving node addbit^sum is itself undriven.WARNING (5)::NETLIST_ERROR Net addbit^co driving node addbit^co is itself undriven.--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_comment.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: addbit==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_half_adder_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_half_adder_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_half_adder_gates.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: half_adder_gates==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.5ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_GrayCounterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_GrayCounter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_GrayCounter.v::24 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '}' or ',') BinaryCount <= {COUNTER_WIDTH{1'b 0}} + 1; //Gray count begins @ '1' withERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_scopesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v::7 error in parsing: (syntax error, unexpected netREG) reg [15:0] x;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v::10 error in parsing: (syntax error, unexpected vEND) endERROR (4)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/scopes.v::16 Function already has input with this name x input [15:0] x, y;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::514
name: asicworld_code_tidbits_asyn_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_asyn_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_asyn_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: asyn_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_paramodsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR Found multiple top level modules pm_test1 pm_test2 pm_test3Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_hierarchydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierarchy.v::2 error in parsing: (syntax error, unexpected '(', expecting vMODULE or preDEFAULT_NETTYPE)(* top *)ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: memories_firrtl_938description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/firrtl_938.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/firrtl_938.v::20 You've defined the driver "q_a~0" twice endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_registered_assignment::3662
name: errors_syntax_err07description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err07.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err07.v::4 error in parsing: (syntax error, unexpected vNUMBER, expecting ';' or ',')assign y = (4)55;
name: simple_arrays01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arrays01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/arrays01.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: uut_arrays01==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.1ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_pri_encoder_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_pri_encoder_using_assign.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: pri_encoder_using_assign==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 8.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.01 seconds (max_rss 7.0 MiB)
name: errors_syntax_err06description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v::4 error in parsing: (syntax error, unexpected vEND)end: label2ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_verilog_tutorial_multiplydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_multiply.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: muliply==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: simple_specifydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/specify.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/specify.v::3 error in parsing: (syntax error, unexpected vSPECPARAM)specparam a=1;ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_undef_eqx_nexdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/undef_eqx_nex.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/undef_eqx_nex.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: undef_eqx_nex==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.9ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_loopsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/loops.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/loops.v::76 You've defined this driver aes^keysched_last_key_i~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: asicworld_code_verilog_tutorial_counter_tbdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v::30 Unsuported tokenevent reset_enable; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v::30 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#')event reset_enable;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v::31 Unsuported tokenevent terminate_sim; ^~~~ERROR (5)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter_tb.v::34 outfile define cannot be found file = $fopen(`outfile);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: asicworld_code_verilog_tutorial_simple_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: errors_syntax_err04description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err04.v::2 error in parsing: (syntax error, unexpected ']')wire [3]x;
name: errors_syntax_err10description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err10.v::2 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or vSIGNED or '[')parameter integer [2:0]x=0;
name: simple_retimedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/retime.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurAssertion failed(node->num_input_pins <= 3)@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/output_blif.cpp]define_logical_function::468
name: asicworld_code_hdl_models_dff_async_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_async_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_dff_async_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: dff_async_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_verilog_tutorial_n_out_primitivedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v::7 Unsuported tokenbuf u_buf0 (out,in); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v::7 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#')buf u_buf0 (out,in);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v::9 Unsuported tokenbuf u_buf1 (out_0, out_1, out_2, out_3, in); ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_n_out_primitive.v::11 error in parsing: (syntax error, unexpected ',')not u_not0 (out_a, out_b, out_c, in);
name: memories_no_implicit_endescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/no_implicit_en.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/memories/no_implicit_en.v::17 error in parsing: (syntax error, unexpected ':') mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[cp_addr][ 7: 0];ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_hdl_models_decoder_using_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_case.v::41 You've defined this driver decoder_using_case^decoder_out~0 twice. Note that Odin II does not currently support combinational a = ? overiding for if and case blocks.endAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_continuous_assignment::3792
name: simple_always03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always03.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/always03.v::20 You've defined the driver "out1" twiceendAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]terminate_registered_assignment::3662
name: asicworld_code_tidbits_fsm_using_single_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_fsm_using_single_always.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: fsm_using_single_always==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_i2c_master_testsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/i2c_master_tests.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR Found multiple top level modules i2c_test01 i2c_test02Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: errors_syntax_err01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err01.v::2 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID)integer [31:0]w;
name: asicworld_code_tidbits_syn_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_syn_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_tidbits_syn_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: syn_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: errors_syntax_err03description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err03.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err03.v::3 error in parsing: (syntax error, unexpected ']') input [3]xERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: simple_graphtestdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/graphtest.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/graphtest.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: graphtest==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 2.3ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.1 MiB)
name: asicworld_code_hdl_models_one_hot_cntdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_one_hot_cnt.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_one_hot_cnt.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: one_hot_cnt==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 2.1ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_tff_async_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_async_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_async_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: tff_async_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: asicworld_code_hdl_models_gray_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_gray_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_gray_counter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: gray_counter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 3.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: asicworld_code_hdl_models_parity_using_bitwisedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_parity_using_bitwise.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurAssertion failed(node->num_input_pins <= 3)@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/output_blif.cpp]define_logical_function::468
name: asicworld_code_hdl_models_encoder_4to2_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_4to2_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: simple_memorydescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::6 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')reg mem [1:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::49 error in parsing: (syntax error, unexpected '(')(* mem2reg *)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::132 error in parsing: (syntax error, unexpected vPLUS_COLON) if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::160 error in parsing: (syntax error, unexpected '(') (* gentb_constant=0 *) wire rst;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::192 error in parsing: (syntax error, unexpected vPLUS_COLON) mem[addr][woffset +: 4] <= wdata;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/memory.v::301 error in parsing: (syntax error, unexpected ':') mem[a2][14:11] <= din2;ERROR (8)::NETLIST_ERROR Found multiple top level modules memtest00 memtest01 memtest02 memtest03 memtest04 memtest05 memtest06_async memtest07 memtest09 memtest10 memtest11 memtest12Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: asicworld_code_hdl_models_tff_sync_resetdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_sync_reset.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_tff_sync_reset.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: tff_sync_reset==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.7ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: errors_syntax_err11description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err11.v']should_fail: 1tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err11.v::2 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or vSIGNED or '[')parameter integer real x=0;
name: asicworld_code_verilog_tutorial_escape_iddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_escape_id.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_escape_id.v::3 error in parsing: (syntax error, unexpected vNUMBER, expecting vSYMBOL_ID)module \1dff (ERROR (3)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: asicworld_code_verilog_tutorial_counterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_counter.v to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: counter==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 1.2ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 7.0 MiB)
name: simple_sincosdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/sincos.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/sincos.v::31 Odin does not handle signed ports (cos_z0)output signed [19:0] cos_z0;Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::690
name: simple_realexprdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::4 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') localparam [7:0] p1 = 123.45;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::5 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') localparam real p2 = 123.45;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::6 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') localparam real p3 = 123;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::7 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') localparam p4 = 123.45;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::9 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y1 = p1 + 0.2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::10 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y2 = p2 + 0.2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::11 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y3 = p3 + 0.2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::12 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y4 = p4 + 0.2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::18 error in parsing: (syntax error, unexpected '.') assign y0 = 1'bx >= (-1 * -1.17);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::19 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::20 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::25 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') parameter real p = 0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::26 error in parsing: (syntax error, unexpected '.') assign A = (p==1.0);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/realexpr.v::31 error in parsing: (syntax error, unexpected '.', expecting ')' or ',') demo_003 #(1.0) demo_real (A, B);ERROR (16)::NETLIST_ERROR Found multiple top level modules demo_001 demo_002 demo_004Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_forgen01description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen01.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/forgen01.v::15 Unsupported condition node in for loop for (j = 2; j*j <= i; j = j+1)Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/ast_loop_unroll.cpp]resolve_for::152
name: simple_wandwordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/wandwor.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurERROR (2)::NETLIST_ERROR Found multiple top level modules wandwor_test0 wandwor_test1Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: asicworld_code_hdl_models_decoder_using_assigndescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_decoder_using_assign.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occur
name: simple_hierdefparamdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v::4 error in parsing: (syntax error, unexpected vBEGIN) generate begin:fooPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v::8 error in parsing: (syntax error, unexpected '[', expecting '=') defparam foo.mod_a.bar[1].mod_b.addvalue = 43;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v::19 error in parsing: (syntax error, unexpected '.', expecting '=') assign bar[0].a = A, bar[1].a = bar[0].y, Y = bar[1].y;ERROR (5)::NETLIST_ERROR Found multiple top level modules hierdefparam_top hierdefparam_aAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::299
name: simple_valuesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:33: warning: extra digits given for sized hex constant./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:33: warning: Numeric constant truncated to 16 bits./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:34: warning: extra digits given for sized octal constant./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:34: warning: Numeric constant truncated to 16 bits./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/values.v:35: warning: Numeric constant truncated to 16 bits.
name: asicworld_code_specman_switch_fabricdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:37: warning: Port 4 (data_in_valid) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:37: : Pruning 7 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:37: warning: Port 6 (data_out_ack) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:37: : Padding 7 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:41: warning: Port 4 (data_in_valid) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:41: : Pruning 7 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:41: warning: Port 6 (data_out_ack) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:41: : Padding 7 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:45: warning: Port 4 (data_in_valid) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:45: : Pruning 7 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:45: warning: Port 6 (data_out_ack) of switch expects 1 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_specman_switch_fabric.v:45: : Padding 7 high bits of the expression.
name: simple_paramodsdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:8: warning: Port 1 (in) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:8: : Pruning 4 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:8: warning: Port 2 (out) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:8: : Padding 4 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:19: warning: Port 1 (in) of inc expects 5 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:19: : Pruning 3 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:19: warning: Port 2 (out) of inc expects 5 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:19: : Padding 3 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:20: warning: Port 1 (in) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:20: : Pruning 4 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:20: warning: Port 2 (out) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:20: : Padding 4 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:32: warning: Port 1 (in) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:32: : Pruning 4 high bits of the expression./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:32: warning: Port 2 (out) of inc expects 4 bits, got 8./home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/paramods.v:32: : Padding 4 high bits of the expression.
name: errors_syntax_err06description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v:4: error: End label doesn't match begin name
name: simple_hierdefparamdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/hierdefparam.v:4: warning: Anachronistic use of named begin/end to surround generate schemes.
name: hana_test_parserdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 1macro expansion of parvez at /home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parser.v:33:11: Parse error: unexpected token 'ahmad' (Id_simple).
name: hana_test_simulation_shifterdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_shifter.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( IN, SHIFT, OUT); input [15:0] IN; input [4:0] SHIFT; output [15:0] OUT; assign OUT = (IN << SHIFT);endmodulemodule f2_test ( IN, SHIFT, OUT); input [31:0] IN; input [5:0] SHIFT; output [31:0] OUT; assign OUT = (IN << SHIFT);endmodulemodule f3_test ( IN, SHIFT, OUT); input [3:0] IN; input [2:0] SHIFT; output [3:0] OUT; assign OUT = (IN << SHIFT);endmodulemodule f4_test ( IN, SHIFT, OUT); input [63:0] IN; input [6:0] SHIFT; output [63:0] OUT; assign OUT = (IN << SHIFT);endmodulemodule f5_test ( IN, SHIFT, OUT); input [7:0] IN; input [3:0] SHIFT; output [7:0] OUT; assign OUT = (IN << SHIFT);endmodulemodule f6_test ( IN, SHIFT, OUT); input [15:0] IN; input [4:0] SHIFT; output [15:0] OUT; assign OUT = (IN >> SHIFT);endmodulemodule f7_test ( IN, SHIFT, OUT); input [31:0] IN; input [5:0] SHIFT; output [31:0] OUT; assign OUT = (IN >> SHIFT);endmodulemodule f8_test ( IN, SHIFT, OUT); input [3:0] IN; input [2:0] SHIFT; output [3:0] OUT; assign OUT = (IN >> SHIFT);endmodulemodule f9_test ( IN, SHIFT, OUT); input [63:0] IN; input [6:0] SHIFT; output [63:0] OUT; assign OUT = (IN >> SHIFT);endmodulemodule f10_test ( IN, SHIFT, OUT); input [7:0] IN; input [3:0] SHIFT; output [7:0] OUT; assign OUT = (IN >> SHIFT);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_seqdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_seq.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, clk, out); input in; input clk; output reg out; always @(posedge clk) out <= in;endmodulemodule f2_test ( in, clk, out); input in; input clk; output reg out; always @(negedge clk) out <= in;endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_decoderdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_decoder.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, enable, out); input [1:0] in; input enable; output reg out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 0; 2'b01: out = 1; 2'b10: out = 0; 2'b11: out = 1; endcase endendmodulemodule f2_test ( in, enable, out); input [1:0] in; input enable; output reg [2:0] out; always @(in or enable) if ((! enable)) out = 3'b000; else begin case (in) 2'b00: out = 3'b001; 2'b01: out = 3'b010; 2'b10: out = 3'b010; 2'b11: out = 3'b100; endcase endendmodulemodule f3_test ( in, out); input [2:0] in; output reg [7:0] out; always @(in) case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcaseendmodulemodule f4_test ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcaseendmodulemodule f5_test ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule f6_test ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule f7_test ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_muxdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_mux.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule f2_test ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule f3_test ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule f4_test ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule f5_test ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule f6_test ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_incdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_inc.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [15:0] in; output [15:0] out; assign out = (- in);endmodulemodule f2_test ( in, out); input in; output out; assign out = (- in);endmodulemodule f3_test ( in, out); input [1:0] in; output [1:0] out; assign out = (- in);endmodulemodule f4_test ( in, out); input [31:0] in; output [31:0] out; assign out = (- in);endmodulemodule f5_test ( in, out); input [3:0] in; output [3:0] out; assign out = (- in);endmodulemodule f6_test ( in, out); input [7:0] in; output [7:0] out; assign out = (- in);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_techmap_techdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap_tech.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_TECH_AND18 ( in, out); input [17:0] in; output out; assign out = (& in);endmodulemodule f1_TECH_AND4 ( in, out); input [3:0] in; output out; assign out = (& in);endmodulemodule f2_TECH_AND5 ( in, out); input [4:0] in; output out; assign out = (& in);endmodulemodule f3_TECH_NAND18 ( in, out); input [17:0] in; output out; assign out = (~ (& in));endmodulemodule f3_TECH_NAND4 ( in, out); input [3:0] in; output out; assign out = (~ (& in));endmodulemodule f3_TECH_NAND2 ( in, out); input [1:0] in; output out; assign out = (~ (& in));endmodulemodule f4_TECH_NAND18 ( in, out); input [17:0] in; output out; assign out = (~ (& in));endmodulemodule f4_TECH_NAND4 ( in, out); input [3:0] in; output out; assign out = (~ (& in));endmodulemodule f4_TECH_NAND2 ( in, out); input [1:0] in; output out; assign out = (~ (& in));endmodulemodule f5_TECH_NAND18 ( in, out); input [17:0] in; output out; assign out = (~ (& in));endmodulemodule f5_TECH_NAND4 ( in, out); input [3:0] in; output out; assign out = (~ (& in));endmodulemodule f5_TECH_NAND2 ( in, out); input [1:0] in; output out; assign out = (~ (& in));endmodulemodule f6_TECH_NOR18 ( in, out); input [17:0] in; output out; assign out = (~ (| in));endmodulemodule f6_TECH_NOR4 ( in, out); input [3:0] in; output out; assign out = (~ (| in));endmodulemodule f6_TECH_NOR2 ( in, out); input [1:0] in; output out; assign out = (~ (| in));endmodulemodule f7_TECH_NOR18 ( in, out); input [17:0] in; output out; assign out = (~ (| in));endmodulemodule f7_TECH_NOR4 ( in, out); input [3:0] in; output out; assign out = (~ (| in));endmodulemodule f7_TECH_NOR2 ( in, out); input [1:0] in; output out; assign out = (~ (| in));endmodulemodule f8_TECH_NOR18 ( in, out); input [17:0] in; output out; assign out = (~ (| in));endmodulemodule f8_TECH_NOR4 ( in, out); input [3:0] in; output out; assign out = (~ (| in));endmodulemodule f8_TECH_NOR2 ( in, out); input [1:0] in; output out; assign out = (~ (| in));endmodulemodule f9_TECH_OR18 ( in, out); input [17:0] in; output out; assign out = (| in);endmodulemodule f9_TECH_OR4 ( in, out); input [3:0] in; output out; assign out = (| in);endmodulemodule f10_TECH_OR5 ( in, out); input [4:0] in; output out; assign out = (| in);endmodulemodule f11_TECH_XOR5 ( in, out); input [4:0] in; output out; assign out = ((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]);endmodulemodule f11_TECH_XOR2 ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule f12_TECH_XOR5 ( in, out); input [4:0] in; output out; assign out = ((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]);endmodulemodule f12_TECH_XOR2 ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule f13_TECH_XOR2 ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule f14_TECH_XOR5 ( in, out); input [4:0] in; output out; assign out = ((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]);endmodulemodule f14_TECH_XOR2 ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule f15_TECH_XOR5 ( in, out); input [4:0] in; output out; assign out = ((((in[0] ^ in[1]) ^ in[2]) ^ in[3]) ^ in[4]);endmodulemodule f15_TECH_XOR2 ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_sopdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_sop.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule f2_test ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule f3_test ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule f4_test ( in, out); input [7:0] in; output out; assign out = (~^ in);endmodulemodule f5_test ( in, out); input in; output out; assign out = (~ in);endmodulemodule f6_test ( in, out); input in; output out; assign out = in;endmodulemodule f7_test (out); output out; assign out = 1'b0;endmodulemodule f8_test ( in, out); input in; output out; assign out = (~ in);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_xnordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xnor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (~ (in[0] ^ in[1]));endmodulemodule f2_test ( in, out); input [2:0] in; output out; assign out = (~ ((in[0] ^ in[1]) ^ in[2]));endmodulemodule f3_test ( in, out); input [3:0] in; output out; assign out = (~ (((in[0] ^ in[1]) ^ in[2]) ^ in[3]));endmodulemodule f4_test ( in, out); input [3:0] in; output out; xnor myxnor (out, in[0], in[1], in[2], in[3]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_intermoutdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_intermout.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( a, b, c, d, z); input a; input b; input c; input d; output z; reg z; reg temp1; reg temp2; always @(a or b or c or d) begin temp1 = (a ^ b); temp2 = (c ^ d); z = (temp1 ^ temp2); endendmodulemodule f2_test ( in1, in2, out); input in1; input in2; output reg out; always @(in1 or in2) if ((in1 > in2)) out = in1; else out = in2;endmodulemodule f3_test ( a, b, c); input b; input c; output reg a; always @(b or c) begin a = b; a = c; endendmodulemodule f4_test ( ctrl, in1, in2, out); input ctrl; input in1; input in2; output reg out; always @(ctrl or in1 or in2) if (ctrl) out = (in1 & in2); else out = (in1 | in2);endmodulemodule f5_NonBlockingEx ( clk, merge, er, xmit, fddi, claim); input clk; input merge; input er; input xmit; input fddi; output reg claim; reg fcr; always @(posedge clk) begin fcr = (er | xmit); if (merge) claim = (fcr & fddi); else claim = fddi; endendmodulemodule f6_FlipFlop ( clk, cs, ns); input clk; input [31:0] cs; output [31:0] ns; integer is; always @(posedge clk) is <= cs; assign ns = is;endmodulemodule f7_FlipFlop ( clock, cs, ns); input clock; input [3:0] cs; output reg [3:0] ns; reg [3:0] temp; always @(posedge clock) begin temp = cs; ns = temp; endendmodulemodule f8_inc ( clock, counter); input clock; output reg [3:0] counter; always @(posedge clock) counter <= (counter + 1);endmodulemodule f9_NegEdgeClock ( q, d, clk, reset); input d; input clk; input reset; output reg q; always @(negedge clk or negedge reset) if ((! reset)) q <= 1'b0; else q <= d;endmodulemodule f10_MyCounter ( clock, preset, updown, presetdata, counter); input clock; input preset; input updown; input [1:0] presetdata; output reg [1:0] counter; always @(posedge clock) if (preset) counter <= presetdata; else if (updown) counter <= (counter + 1); else counter <= (counter - 1);endmodulemodule f11_test ( en, in, out); input en; input [1:0] in; output reg [2:0] out; always @(en or in) if (en) out = (in + 1);endmodulemodule f12_test ( in, out); input in; output out; assign out = in;endmodulemodule f13_test ( in, out); input in; output out; wire w1; wire w2; assign w1 = in; assign w2 = w1; assign out = w2;endmodulemodule f14_test ( in, out); input in; output out; wire w1; wire w2; wire w3; wire w4; assign w1 = in; assign w2 = w1; assign w4 = w3; assign out = w4; f14_mybuf _f14_mybuf( w2, w3 );endmodulemodule f14_mybuf ( in, out); input in; output out; wire w1; wire w2; wire w3; wire w4; assign w1 = in; assign w2 = w1; assign out = w2;endmodulemodule f15_test ( in1, in2, out); input in1; input in2; output out; wire w1; wire w2; wire w3; wire w4; wire w5; wire w6; wire w7; wire w8; wire w9; wire w10; assign w1 = in1; assign w2 = w1; assign w5 = in2; assign w6 = w5; assign w10 = w9; assign out = w10; f15_mybuf _f15_mybuf0( w2, w3 ); f15_mybuf _f15_mybuf1( w3, w4 ); f15_mybuf _f15_mybuf2( w6, w7 ); f15_mybuf _f15_mybuf3( w7, w4 ); f15_mybuf _f15_mybuf4( w4, w8 ); f15_mybuf _f15_mybuf5( w8, w9 );endmodulemodule f15_mybuf ( in, out); input in; output out; wire w1; wire w2; wire w3; wire w4; assign w1 = in; assign w2 = w1; assign out = w2;endmodulemodule f16_test ( out, in1, in2, vin1, vin2, vout1); output out; input in1; input in2; input [1:0] vin1; input [2:0] vin2; output [3:0] vout1; assign out = (in1 + in2); assign vout1 = (vin1 + vin2);endmodulemodule f17_test ( in1, in2, vin1, vin2, out, vout, vin3, vin4, vout1); input in1; input in2; input [1:0] vin1; input [3:0] vin2; input [1:0] vin3; input [3:0] vin4; output vout; output vout1; output out; assign out = (in1 && in2); assign vout = (vin1 && vin2); assign vout1 = (vin3 || vin4);endmodulemodule f18_test ( out, in, vout, vin); output out; input in; output [1:0] vout; input [1:0] vin; assign out = (~ in); assign vout = (~ vin);endmodulemodule f19_buffer ( in, out, vin, vout); input in; output out; input [1:0] vin; output [1:0] vout; assign out = in; assign vout = vin;endmodulemodule f20_test ( in1, in2, out, vin1, vin2, vin3, vin4, vout1, vout2, en1, ven1, ven2); input in1; input in2; input en1; input ven1; input [1:0] ven2; output out; input [1:0] vin1; input [1:0] vin2; input [1:0] vin3; input [1:0] vin4; output [1:0] vout1; output [1:0] vout2; assign out = (en1 ? in1 : in2); assign vout1 = (ven1 ? vin1 : vin2); assign vout2 = (ven2 ? vin3 : vin4);endmodulemodule f21_test ( in, out, en, vin1, vout1, en1); input in; input en; input en1; output out; input [1:0] vin1; output [1:0] vout1; assign out = (en ? in : 1'bz); assign vout1 = (en1 ? vin1 : 2'bzz);endmodulemodule f22_test ( in, out, vin, vout, vin1, vout1, vin2, vout2); input in; input [3:0] vin; input [3:0] vin1; input [3:0] vin2; output [3:0] vout; output [3:0] vout1; output [3:0] vout2; output out; assign out = (in << 1); assign vout = (vin << 2); assign vout1 = (vin1 >> 2); assign vout2 = (vin2 >>> 2);endmodulemodule f23_test ( out, vout); output out; output [7:0] vout; assign out = 1'b1; assign vout = 9;endmodulemodule f24_test ( out, in1, in2, vin1, vin2, vout1); output out; input in1; input in2; input [1:0] vin1; input [2:0] vin2; output [3:0] vout1; assign out = (in1 / in2); assign vout1 = (vin1 / vin2);endmodulemodule f25_test ( out, vout, in, vin); output out; output vout; input in; input [3:0] vin; assign out = (! in); assign vout = (! vin);endmodulemodule f26_test ( out, in1, in2, vin1, vin2, vout1); output out; input in1; input in2; input [1:0] vin1; input [2:0] vin2; output [3:0] vout1; assign out = (in1 % in2); assign vout1 = (vin1 % vin2);endmodulemodule f27_test ( out, in1, in2, vin1, vin2, vout1); output out; input in1; input in2; input [1:0] vin1; input [2:0] vin2; output [3:0] vout1; assign out = (in1 * in2); assign vout1 = (vin1 * vin2);endmodulemodule f28_test ( out, vin, out1, vin1); output out; input [1:0] vin; output out1; input [3:0] vin1; assign out = (& vin); assign out1 = (& vin1);endmodulemodule f29_Reduction ( A1, A2, A3, A4, A5, A6, Y1, Y2, Y3, Y4, Y5, Y6); input [1:0] A1; input [1:0] A2; input [1:0] A3; input [1:0] A4; input [1:0] A5; input [1:0] A6; output Y1; output Y2; output Y3; output Y4; output Y5; output Y6; assign Y1 = (& A1); assign Y2 = (| A2); assign Y3 = (~& A3); assign Y4 = (~| A4); assign Y5 = (^ A5); assign Y6 = (~^ A6);endmodulemodule f30_test ( out, in1, in2, vin1, vin2, vout1); output out; input in1; input in2; input [1:0] vin1; input [2:0] vin2; output [3:0] vout1; assign out = (in1 - in2); assign vout1 = (vin1 - vin2);endmodulemodule f31_test ( out, in, vout, vin); output out; input in; output [31:0] vout; input [31:0] vin; assign out = (- in); assign vout = (- vin);endmodulemodule f32_test ( out, in); output out; input in; assign out = (+ in);endmodulemodule f33_test ( vin0, vout0); input [2:0] vin0; output wire [7:0] vout0; wire [7:0] myreg0; wire [7:0] myreg1; wire [7:0] myreg2; integer i; assign myreg0 = (vout0 << vin0); assign myreg1 = (myreg2 >> i);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_xordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_xor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (in[0] ^ in[1]);endmodulemodule f2_test ( in, out); input [2:0] in; output out; assign out = ((in[0] ^ in[1]) ^ in[2]);endmodulemodule f3_test ( in, out); input [3:0] in; output out; assign out = (((in[0] ^ in[1]) ^ in[2]) ^ in[3]);endmodulemodule f4_test ( in, out); input [3:0] in; output out; xor myxor (out, in[0], in[1], in[2], in[3]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_bufferdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_buffer.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input in; output out; assign out = in;endmodulemodule f2_test ( in, out); input [1:0] in; output [1:0] out; assign out[0] = in[0]; assign out[1] = in[1];endmodulemodule f3_test ( in, out); input in; output [1:0] out; assign out[0] = in; assign out[1] = in;endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_parse2synthtransdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_parse2synthtrans.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out, clk, reset); input in; input reset; output wire out; input clk; reg signed [3:0] a; reg signed [3:0] b; reg signed [3:0] c; reg [5:0] d; reg [5:0] e; always @(clk or reset) begin a = (- 4); b = 2; c = (a + b); d = ((a + b) + c); d = (d * d); if (b) e = (d * d); else e = (d + d); endendmodulemodule f2_demultiplexer1_to_4 ( out0, out1, out2, out3, in, s1, s0); output out0; output out1; output out2; output out3; wire out0; wire out1; wire out2; wire out3; input in; input s1; input s0; wire [3:0] encoding; reg [1:0] state; always @(encoding) begin case (encoding) 4'bxx11: state = 1; 4'bx0xx: state = 3; 4'b11xx: state = 4; 4'bx1xx: state = 2; 4'bxx1x: state = 1; 4'bxxx1: state = 0; default: state = 0; endcase end always @(encoding) begin case (encoding) 4'b0000: state = 1; default: state = 0; endcase endendmodulemodule f3_test ( in, out); input wire in; output out; assign out = (in + in); assign out = 74;endmodulemodule f4_test; endmodulemodule f5_test ( in, out); input in; output out; parameter p1 = 10; parameter p2 = 5; assign out = (+ p1); assign out = (- p2); assign out = (p1 + p2); assign out = (p1 - p2);endmodulemodule f6_test ( in, out); input in; output out; parameter p = 10; assign out = p;endmodulemodule f7_test ( in, out, io); inout io; output out; input in;endmodulemodule f8_test ( in1, in2, out1, out2, io1, io2); inout [1:0] io1; inout [0:1] io2; output [1:0] out1; output [0:1] out2; input [1:0] in1; input [0:1] in2;endmodulemodule f9_test ( q, d, clk, reset); output reg q; input d; input clk; input reset; always @(posedge clk or negedge reset) if ((! reset)) q <= 0; else q <= d;endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_nanddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nand.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (~ (in[0] & in[1]));endmodulemodule f2_test ( in, out); input [2:0] in; output out; assign out = (! ((in[0] & in[1]) & in[2]));endmodulemodule f3_test ( in, out); input [2:0] in; output out; assign out = (~ ((in[0] && in[1]) && in[2]));endmodulemodule f4_test ( in, out); input [3:0] in; output out; assign out = (! (((in[0] & in[1]) & in[2]) & in[3]));endmodulemodule f5_test ( in, out); input [3:0] in; output out; assign out = (! (((in[0] && in[1]) && in[2]) && in[3]));endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_anddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_and.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (in[0] & in[1]);endmodulemodule f2_test ( in, out); input [1:0] in; output out; assign out = (in[0] && in[1]);endmodulemodule f3_test ( in, out); input [2:0] in; output out; assign out = ((in[0] & in[1]) & in[2]);endmodulemodule f4_test ( in, out); input [2:0] in; output out; assign out = ((in[0] && in[1]) && in[2]);endmodulemodule f5_test ( in, out); input [3:0] in; output out; assign out = (((in[0] & in[1]) & in[2]) & in[3]);endmodulemodule f6_test ( in, out); input [3:0] in; output out; assign out = (((in[0] && in[1]) && in[2]) && in[3]);endmodulemodule f7_test ( in, out); input [3:0] in; output out; and myand (out, in[0], in[1], in[2], in[3]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_always.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output reg [1:0] out; always @(in) out = in;endmodulemodule f2_test ( a, b, c, d, z); input a; input b; input c; input d; output z; reg z; reg temp1; reg temp2; always @(a or b or c or d) begin temp1 = (a ^ b); temp2 = (c ^ d); z = (temp1 ^ temp2); endendmodulemodule f3_test ( in1, in2, out); input in1; input in2; output reg out; always @(in1 or in2) if ((in1 > in2)) out = in1; else out = in2;endmodulemodule f4_test ( ctrl, in1, in2, out); input ctrl; input in1; input in2; output reg out; always @(ctrl or in1 or in2) if (ctrl) out = (in1 & in2); else out = (in1 | in2);endmodulemodule f5_test ( in, out); input in; output reg out; always @(in) out = in;endmodulemodule f6_NonBlockingEx ( clk, merge, er, xmit, fddi, claim); input clk; input merge; input er; input xmit; input fddi; output reg claim; reg fcr; always @(posedge clk) begin fcr <= (er | xmit); if (merge) claim <= (fcr & fddi); else claim <= fddi; endendmodulemodule f7_FlipFlop ( clk, cs, ns); input clk; input [7:0] cs; output [7:0] ns; integer is; always @(posedge clk) is <= cs; assign ns = is;endmodulemodule f8_inc ( clock, counter); input clock; output reg [7:0] counter; always @(posedge clock) counter <= (counter + 1);endmodulemodule f9_MyCounter ( clock, preset, updown, presetdata, counter); input clock; input preset; input updown; input [1:0] presetdata; output reg [1:0] counter; always @(posedge clock) if (preset) counter <= presetdata; else if (updown) counter <= (counter + 1); else counter <= (counter - 1);endmodulemodule f10_FlipFlop ( clock, cs, ns); input clock; input cs; output reg ns; reg temp; always @(posedge clock) begin temp <= cs; ns <= temp; endendmodulemodule f11_test ( in, out); input in; output reg [1:0] out; always @(in) begin out = in; out = (out + in); endendmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_nordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_nor.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (~ (in[0] | in[1]));endmodulemodule f2_test ( in, out); input [2:0] in; output out; assign out = (~ ((in[0] | in[1]) | in[2]));endmodulemodule f3_test ( in, out); input [3:0] in; output out; assign out = (~ (((in[0] | in[1]) | in[2]) | in[3]));endmodulemodule f4_test ( in, out); input [3:0] in; output out; nor mynor (out, in[0], in[1], in[2], in[3]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_techmapdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_techmap.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input in; output out; assign out = in;endmodulemodule f2_test ( in, out); input in; output out; assign out = (~ in);endmodulemodule f3_test ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule f4_test ( in, select, out); input [127:0] in; input [6:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; 64: out = in[64]; 65: out = in[65]; 66: out = in[66]; 67: out = in[67]; 68: out = in[68]; 69: out = in[69]; 70: out = in[70]; 71: out = in[71]; 72: out = in[72]; 73: out = in[73]; 74: out = in[74]; 75: out = in[75]; 76: out = in[76]; 77: out = in[77]; 78: out = in[78]; 79: out = in[79]; 80: out = in[80]; 81: out = in[81]; 82: out = in[82]; 83: out = in[83]; 84: out = in[84]; 85: out = in[85]; 86: out = in[86]; 87: out = in[87]; 88: out = in[88]; 89: out = in[89]; 90: out = in[90]; 91: out = in[91]; 92: out = in[92]; 93: out = in[93]; 94: out = in[94]; 95: out = in[95]; 96: out = in[96]; 97: out = in[97]; 98: out = in[98]; 99: out = in[99]; 100: out = in[100]; 101: out = in[101]; 102: out = in[102]; 103: out = in[103]; 104: out = in[104]; 105: out = in[105]; 106: out = in[106]; 107: out = in[107]; 108: out = in[108]; 109: out = in[109]; 110: out = in[110]; 111: out = in[111]; 112: out = in[112]; 113: out = in[113]; 114: out = in[114]; 115: out = in[115]; 116: out = in[116]; 117: out = in[117]; 118: out = in[118]; 119: out = in[119]; 120: out = in[120]; 121: out = in[121]; 122: out = in[122]; 123: out = in[123]; 124: out = in[124]; 125: out = in[125]; 126: out = in[126]; 127: out = in[127]; endcaseendmodulemodule f5_test ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_vlibdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_vlib.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in1, in2, out); input in1; input in2; output out; wire synth_net_0; wire synth_net_1; BUF synth_BUF_0( .in(synth_net_1), .out(out) ); DIV1 synth_DIV( .in1(in1), .in2(in2), .rem(synth_net_0), .out(synth_net_1) );endmodulemodule f2_test ( clk, cond, data); input cond; input clk; output data; wire synth_net; wire synth_net_0; wire synth_net_1; wire synth_net_2; wire synth_net_3; wire synth_net_4; wire synth_net_5; wire synth_net_6; wire synth_net_7; wire synth_net_8; wire synth_net_9; wire synth_net_10; wire synth_net_11; wire tmp; AND2 synth_AND( .in({synth_net_0, synth_net_1}), .out(synth_net_2) ); AND2 synth_AND_0( .in({synth_net_3, synth_net_4}), .out(synth_net_5) ); AND2 synth_AND_1( .in({synth_net_6, synth_net_7}), .out(synth_net_8) ); AND2 synth_AND_2( .in({synth_net_9, synth_net_10}), .out(synth_net_11) ); BUF synth_BUF( .in(synth_net), .out(synth_net_0) ); BUF synth_BUF_0( .in(data), .out(synth_net_3) ); BUF synth_BUF_1( .in(synth_net_8), .out(tmp) ); BUF synth_BUF_2( .in(tmp), .out(synth_net_9) ); MUX2 synth_MUX( .in({synth_net_2, synth_net_5}), .select(cond), .out(synth_net_6) ); MUX2 synth_MUX_0( .in({synth_net_1, synth_net_4}), .select(cond), .out(synth_net_7) ); FF synth_FF( .d(synth_net_11), .clk(clk), .q(data) ); VCC synth_VCC(.out(synth_net)); VCC synth_VCC_0(.out(synth_net_1)); VCC synth_VCC_1(.out(synth_net_4)); VCC synth_VCC_2(.out(synth_net_10));endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: hana_test_simulation_ordescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/test_simulation_or.v', '/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/hana/hana_vlib.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module f1_test ( in, out); input [1:0] in; output out; assign out = (in[0] | in[1]);endmodulemodule f2_test ( in, out); input [1:0] in; output out; assign out = (in[0] || in[1]);endmodulemodule f3_test ( in, out); input [2:0] in; output out; assign out = ((in[0] | in[1]) | in[2]);endmodulemodule f4_test ( in, out); input [2:0] in; output out; assign out = ((in[0] || in[1]) || in[2]);endmodulemodule f5_test ( in, out); input [3:0] in; output out; assign out = (((in[0] | in[1]) | in[2]) | in[3]);endmodulemodule f6_test ( in, out); input [3:0] in; output out; assign out = (((in[0] || in[1]) || in[2]) || in[3]);endmodulemodule BUF ( in, out); input in; output out; assign out = in;endmodulemodule TRIBUF ( in, enable, out); input in; input enable; output out; assign out = (enable ? in : 1'bz);endmodulemodule INV ( in, out); input in; output out; assign out = (~ in);endmodulemodule AND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule AND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (& in);endmodulemodule OR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule OR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (| in);endmodulemodule NAND2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NAND4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~& in);endmodulemodule NOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule NOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~| in);endmodulemodule XOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (^ in);endmodulemodule XNOR2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR3 ( in, out); parameter SIZE = 3; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule XNOR4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output out; assign out = (~^ in);endmodulemodule DEC1 ( in, enable, out); input in; input enable; output reg [1:0] out; always @(in or enable) if ((! enable)) out = 2'b00; else begin case (in) 1'b0: out = 2'b01; 1'b1: out = 2'b10; endcase endendmodulemodule DEC2 ( in, enable, out); input [1:0] in; input enable; output reg [3:0] out; always @(in or enable) if ((! enable)) out = 4'b0000; else begin case (in) 2'b00: out = 4'b0001; 2'b01: out = 4'b0010; 2'b10: out = 4'b0100; 2'b11: out = 4'b1000; endcase endendmodulemodule DEC3 ( in, enable, out); input [2:0] in; input enable; output reg [7:0] out; always @(in or enable) if ((! enable)) out = 8'b00000000; else begin case (in) 3'b000: out = 8'b00000001; 3'b001: out = 8'b00000010; 3'b010: out = 8'b00000100; 3'b011: out = 8'b00001000; 3'b100: out = 8'b00010000; 3'b101: out = 8'b00100000; 3'b110: out = 8'b01000000; 3'b111: out = 8'b10000000; endcase endendmodulemodule DEC4 ( in, enable, out); input [3:0] in; input enable; output reg [15:0] out; always @(in or enable) if ((! enable)) out = 16'b0000000000000000; else begin case (in) 4'b0000: out = 16'b0000000000000001; 4'b0001: out = 16'b0000000000000010; 4'b0010: out = 16'b0000000000000100; 4'b0011: out = 16'b0000000000001000; 4'b0100: out = 16'b0000000000010000; 4'b0101: out = 16'b0000000000100000; 4'b0110: out = 16'b0000000001000000; 4'b0111: out = 16'b0000000010000000; 4'b1000: out = 16'b0000000100000000; 4'b1001: out = 16'b0000001000000000; 4'b1010: out = 16'b0000010000000000; 4'b1011: out = 16'b0000100000000000; 4'b1100: out = 16'b0001000000000000; 4'b1101: out = 16'b0010000000000000; 4'b1110: out = 16'b0100000000000000; 4'b1111: out = 16'b1000000000000000; endcase endendmodulemodule DEC5 ( in, enable, out); input [4:0] in; input enable; output reg [31:0] out; always @(in or enable) if ((! enable)) out = 32'b00000000000000000000000000000000; else begin case (in) 5'b00000: out = 32'b00000000000000000000000000000001; 5'b00001: out = 32'b00000000000000000000000000000010; 5'b00010: out = 32'b00000000000000000000000000000100; 5'b00011: out = 32'b00000000000000000000000000001000; 5'b00100: out = 32'b00000000000000000000000000010000; 5'b00101: out = 32'b00000000000000000000000000100000; 5'b00110: out = 32'b00000000000000000000000001000000; 5'b00111: out = 32'b00000000000000000000000010000000; 5'b01000: out = 32'b00000000000000000000000100000000; 5'b01001: out = 32'b00000000000000000000001000000000; 5'b01010: out = 32'b00000000000000000000010000000000; 5'b01011: out = 32'b00000000000000000000100000000000; 5'b01100: out = 32'b00000000000000000001000000000000; 5'b01101: out = 32'b00000000000000000010000000000000; 5'b01110: out = 32'b00000000000000000100000000000000; 5'b01111: out = 32'b00000000000000001000000000000000; 5'b10000: out = 32'b00000000000000010000000000000000; 5'b10001: out = 32'b00000000000000100000000000000000; 5'b10010: out = 32'b00000000000001000000000000000000; 5'b10011: out = 32'b00000000000010000000000000000000; 5'b10100: out = 32'b00000000000100000000000000000000; 5'b10101: out = 32'b00000000001000000000000000000000; 5'b10110: out = 32'b00000000010000000000000000000000; 5'b10111: out = 32'b00000000100000000000000000000000; 5'b11000: out = 32'b00000001000000000000000000000000; 5'b11001: out = 32'b00000010000000000000000000000000; 5'b11010: out = 32'b00000100000000000000000000000000; 5'b11011: out = 32'b00001000000000000000000000000000; 5'b11100: out = 32'b00010000000000000000000000000000; 5'b11101: out = 32'b00100000000000000000000000000000; 5'b11110: out = 32'b01000000000000000000000000000000; 5'b11111: out = 32'b10000000000000000000000000000000; endcase endendmodulemodule DEC6 ( in, enable, out); input [5:0] in; input enable; output reg [63:0] out; always @(in or enable) if ((! enable)) out = 64'b0000000000000000000000000000000000000000000000000000000000000000; else begin case (in) 6'b000000: out = 64'b0000000000000000000000000000000000000000000000000000000000000001; 6'b000001: out = 64'b0000000000000000000000000000000000000000000000000000000000000010; 6'b000010: out = 64'b0000000000000000000000000000000000000000000000000000000000000100; 6'b000011: out = 64'b0000000000000000000000000000000000000000000000000000000000001000; 6'b000100: out = 64'b0000000000000000000000000000000000000000000000000000000000010000; 6'b000101: out = 64'b0000000000000000000000000000000000000000000000000000000000100000; 6'b000110: out = 64'b0000000000000000000000000000000000000000000000000000000001000000; 6'b000111: out = 64'b0000000000000000000000000000000000000000000000000000000010000000; 6'b001000: out = 64'b0000000000000000000000000000000000000000000000000000000100000000; 6'b001001: out = 64'b0000000000000000000000000000000000000000000000000000001000000000; 6'b001010: out = 64'b0000000000000000000000000000000000000000000000000000010000000000; 6'b001011: out = 64'b0000000000000000000000000000000000000000000000000000100000000000; 6'b001100: out = 64'b0000000000000000000000000000000000000000000000000001000000000000; 6'b001101: out = 64'b0000000000000000000000000000000000000000000000000010000000000000; 6'b001110: out = 64'b0000000000000000000000000000000000000000000000000100000000000000; 6'b001111: out = 64'b0000000000000000000000000000000000000000000000001000000000000000; 6'b010000: out = 64'b0000000000000000000000000000000000000000000000010000000000000000; 6'b010001: out = 64'b0000000000000000000000000000000000000000000000100000000000000000; 6'b010010: out = 64'b0000000000000000000000000000000000000000000001000000000000000000; 6'b010011: out = 64'b0000000000000000000000000000000000000000000010000000000000000000; 6'b010100: out = 64'b0000000000000000000000000000000000000000000100000000000000000000; 6'b010101: out = 64'b0000000000000000000000000000000000000000001000000000000000000000; 6'b010110: out = 64'b0000000000000000000000000000000000000000010000000000000000000000; 6'b010111: out = 64'b0000000000000000000000000000000000000000100000000000000000000000; 6'b011000: out = 64'b0000000000000000000000000000000000000001000000000000000000000000; 6'b011001: out = 64'b0000000000000000000000000000000000000010000000000000000000000000; 6'b011010: out = 64'b0000000000000000000000000000000000000100000000000000000000000000; 6'b011011: out = 64'b0000000000000000000000000000000000001000000000000000000000000000; 6'b011100: out = 64'b0000000000000000000000000000000000010000000000000000000000000000; 6'b011101: out = 64'b0000000000000000000000000000000000100000000000000000000000000000; 6'b011110: out = 64'b0000000000000000000000000000000001000000000000000000000000000000; 6'b011111: out = 64'b0000000000000000000000000000000010000000000000000000000000000000; 6'b100000: out = 64'b0000000000000000000000000000000100000000000000000000000000000000; 6'b100001: out = 64'b0000000000000000000000000000001000000000000000000000000000000000; 6'b100010: out = 64'b0000000000000000000000000000010000000000000000000000000000000000; 6'b100011: out = 64'b0000000000000000000000000000100000000000000000000000000000000000; 6'b100100: out = 64'b0000000000000000000000000001000000000000000000000000000000000000; 6'b100101: out = 64'b0000000000000000000000000010000000000000000000000000000000000000; 6'b100110: out = 64'b0000000000000000000000000100000000000000000000000000000000000000; 6'b100111: out = 64'b0000000000000000000000001000000000000000000000000000000000000000; 6'b101000: out = 64'b0000000000000000000000010000000000000000000000000000000000000000; 6'b101001: out = 64'b0000000000000000000000100000000000000000000000000000000000000000; 6'b101010: out = 64'b0000000000000000000001000000000000000000000000000000000000000000; 6'b101011: out = 64'b0000000000000000000010000000000000000000000000000000000000000000; 6'b101100: out = 64'b0000000000000000000100000000000000000000000000000000000000000000; 6'b101101: out = 64'b0000000000000000001000000000000000000000000000000000000000000000; 6'b101110: out = 64'b0000000000000000010000000000000000000000000000000000000000000000; 6'b101111: out = 64'b0000000000000000100000000000000000000000000000000000000000000000; 6'b110000: out = 64'b0000000000000001000000000000000000000000000000000000000000000000; 6'b110001: out = 64'b0000000000000010000000000000000000000000000000000000000000000000; 6'b110010: out = 64'b0000000000000100000000000000000000000000000000000000000000000000; 6'b110011: out = 64'b0000000000001000000000000000000000000000000000000000000000000000; 6'b110100: out = 64'b0000000000010000000000000000000000000000000000000000000000000000; 6'b110101: out = 64'b0000000000100000000000000000000000000000000000000000000000000000; 6'b110110: out = 64'b0000000001000000000000000000000000000000000000000000000000000000; 6'b110111: out = 64'b0000000010000000000000000000000000000000000000000000000000000000; 6'b111000: out = 64'b0000000100000000000000000000000000000000000000000000000000000000; 6'b111001: out = 64'b0000001000000000000000000000000000000000000000000000000000000000; 6'b111010: out = 64'b0000010000000000000000000000000000000000000000000000000000000000; 6'b111011: out = 64'b0000100000000000000000000000000000000000000000000000000000000000; 6'b111100: out = 64'b0001000000000000000000000000000000000000000000000000000000000000; 6'b111101: out = 64'b0010000000000000000000000000000000000000000000000000000000000000; 6'b111110: out = 64'b0100000000000000000000000000000000000000000000000000000000000000; 6'b111111: out = 64'b1000000000000000000000000000000000000000000000000000000000000000; endcase endendmodulemodule MUX2 ( in, select, out); input [1:0] in; input select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; endcaseendmodulemodule MUX4 ( in, select, out); input [3:0] in; input [1:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; endcaseendmodulemodule MUX8 ( in, select, out); input [7:0] in; input [2:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; endcaseendmodulemodule MUX16 ( in, select, out); input [15:0] in; input [3:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; endcaseendmodulemodule MUX32 ( in, select, out); input [31:0] in; input [4:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; endcaseendmodulemodule MUX64 ( in, select, out); input [63:0] in; input [5:0] select; output reg out; always @(in or select) case (select) 0: out = in[0]; 1: out = in[1]; 2: out = in[2]; 3: out = in[3]; 4: out = in[4]; 5: out = in[5]; 6: out = in[6]; 7: out = in[7]; 8: out = in[8]; 9: out = in[9]; 10: out = in[10]; 11: out = in[11]; 12: out = in[12]; 13: out = in[13]; 14: out = in[14]; 15: out = in[15]; 16: out = in[16]; 17: out = in[17]; 18: out = in[18]; 19: out = in[19]; 20: out = in[20]; 21: out = in[21]; 22: out = in[22]; 23: out = in[23]; 24: out = in[24]; 25: out = in[25]; 26: out = in[26]; 27: out = in[27]; 28: out = in[28]; 29: out = in[29]; 30: out = in[30]; 31: out = in[31]; 32: out = in[32]; 33: out = in[33]; 34: out = in[34]; 35: out = in[35]; 36: out = in[36]; 37: out = in[37]; 38: out = in[38]; 39: out = in[39]; 40: out = in[40]; 41: out = in[41]; 42: out = in[42]; 43: out = in[43]; 44: out = in[44]; 45: out = in[45]; 46: out = in[46]; 47: out = in[47]; 48: out = in[48]; 49: out = in[49]; 50: out = in[50]; 51: out = in[51]; 52: out = in[52]; 53: out = in[53]; 54: out = in[54]; 55: out = in[55]; 56: out = in[56]; 57: out = in[57]; 58: out = in[58]; 59: out = in[59]; 60: out = in[60]; 61: out = in[61]; 62: out = in[62]; 63: out = in[63]; endcaseendmodulemodule ADD1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule ADD64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 + in2) + cin);endmodulemodule SUB1 ( in1, in2, cin, out, cout); input in1; input in2; input cin; output out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB2 ( in1, in2, cin, out, cout); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB4 ( in1, in2, cin, out, cout); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB8 ( in1, in2, cin, out, cout); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB16 ( in1, in2, cin, out, cout); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB32 ( in1, in2, cin, out, cout); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule SUB64 ( in1, in2, cin, out, cout); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; input cin; output [(SIZE - 1):0] out; output cout; assign {cout, out} = ((in1 - in2) - cin);endmodulemodule MUL1 ( in1, in2, out); parameter SIZE = 1; input in1; input in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL2 ( in1, in2, out); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL4 ( in1, in2, out); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL8 ( in1, in2, out); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL16 ( in1, in2, out); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL32 ( in1, in2, out); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule MUL64 ( in1, in2, out); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [((2 * SIZE) - 1):0] out; assign out = (in1 * in2);endmodulemodule DIV1 ( in1, in2, out, rem); parameter SIZE = 1; input in1; input in2; output out; output rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV2 ( in1, in2, out, rem); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV4 ( in1, in2, out, rem); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV8 ( in1, in2, out, rem); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV16 ( in1, in2, out, rem); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV32 ( in1, in2, out, rem); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule DIV64 ( in1, in2, out, rem); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output [(SIZE - 1):0] out; output [(SIZE - 1):0] rem; assign out = (in1 / in2); assign rem = (in1 % in2);endmodulemodule FF ( d, clk, q); input d; input clk; output reg q; always @(posedge clk) q <= d;endmodulemodule RFF ( d, clk, reset, q); input d; input clk; input reset; output reg q; always @(posedge clk or posedge reset) if (reset) q <= 0; else q <= d;endmodulemodule SFF ( d, clk, set, q); input d; input clk; input set; output reg q; always @(posedge clk or posedge set) if (set) q <= 1; else q <= d;endmodulemodule RSFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge reset or posedge set) if (reset) q <= 0; else if (set) q <= 1; else q <= d;endmodulemodule SRFF ( d, clk, set, reset, q); input d; input clk; input set; input reset; output reg q; always @(posedge clk or posedge set or posedge reset) if (set) q <= 1; else if (reset) q <= 0; else q <= d;endmodulemodule LATCH ( d, enable, q); input d; input enable; output reg q; always @(d or enable) if (enable) q <= d;endmodulemodule RLATCH ( d, reset, enable, q); input d; input reset; input enable; output reg q; always @(d or enable or reset) if (enable) if (reset) q <= 0; else q <= d;endmodulemodule LSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule LSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule LSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in << shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} >> ((SIZE - 1) - shift))); endendmodulemodule RSHIFT1 ( in, shift, val, out); parameter SIZE = 1; input in; input shift; input val; output reg out; always @(in or shift or val) begin if (shift) out = val; else out = in; endendmodulemodule RSHIFT2 ( in, shift, val, out); parameter SIZE = 2; input [(SIZE - 1):0] in; input [(SIZE - 1):0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT4 ( in, shift, val, out); parameter SIZE = 4; input [(SIZE - 1):0] in; input [2:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT8 ( in, shift, val, out); parameter SIZE = 8; input [(SIZE - 1):0] in; input [3:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT16 ( in, shift, val, out); parameter SIZE = 16; input [(SIZE - 1):0] in; input [4:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT32 ( in, shift, val, out); parameter SIZE = 32; input [(SIZE - 1):0] in; input [5:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule RSHIFT64 ( in, shift, val, out); parameter SIZE = 64; input [(SIZE - 1):0] in; input [6:0] shift; input val; output reg [(SIZE - 1):0] out; always @(in or shift or val) begin out = (in >> shift); if (val) out = (out | ({(SIZE - 1) {1'b1}} << ((SIZE - 1) - shift))); endendmodulemodule CMP1 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 1; input in1; input in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP2 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 2; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP4 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 4; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP8 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 8; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP16 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 16; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP32 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 32; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule CMP64 ( in1, in2, equal, unequal, greater, lesser); parameter SIZE = 64; input [(SIZE - 1):0] in1; input [(SIZE - 1):0] in2; output reg equal; output reg unequal; output reg greater; output reg lesser; always @(in1 or in2) begin if ((in1 == in2)) begin equal = 1; unequal = 0; greater = 0; lesser = 0; end else begin equal = 0; unequal = 1; if ((in1 < in2)) begin greater = 0; lesser = 1; end else begin greater = 1; lesser = 0; end end endendmodulemodule VCC (out); output supply1 out;endmodulemodule GND (out); output supply0 out;endmodulemodule INC1 ( in, out); parameter SIZE = 1; input in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC2 ( in, out); parameter SIZE = 2; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC4 ( in, out); parameter SIZE = 4; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC8 ( in, out); parameter SIZE = 8; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC16 ( in, out); parameter SIZE = 16; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC32 ( in, out); parameter SIZE = 32; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodulemodule INC64 ( in, out); parameter SIZE = 64; input [(SIZE - 1):0] in; output [SIZE:0] out; assign out = (in + 1);endmodule
name: asicworld_code_verilog_tutorial_decoder_alwaysdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_decoder_always.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module decoder_always ( in, out); input [2:0] in; output [7:0] out; reg [7:0] out; always @(in) begin out = 0; case (in) 3'b001: out = 8'b0000_0001; 3'b010: out = 8'b0000_0010; 3'b011: out = 8'b0000_0100; 3'b100: out = 8'b0000_1000; 3'b101: out = 8'b0001_0000; 3'b110: out = 8'b0100_0000; 3'b111: out = 8'b1000_0000; endcase endendmodule
name: errors_syntax_err05description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err05.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1zachjs-sv2v: incomplete declarationCallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:313:21 in main:Language.SystemVerilog.Parser.ParseDecl
name: simple_attrib09_casedescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/attrib09_case.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module bar ( clk, rst, inp, out); input wire clk; input wire rst; input wire [1:0] inp; output reg [1:0] out; always @(inp) (* full_case, parallel_case *) case (inp) 2'd0: out <= 2'd3; 2'd1: out <= 2'd2; 2'd2: out <= 2'd1; 2'd3: out <= 2'd0; endcaseendmodulemodule foo ( clk, rst, inp, out); input wire clk; input wire rst; input wire [1:0] inp; output wire [1:0] out; bar bar_instance( clk, rst, inp, out );endmodule
name: asicworld_code_hdl_models_encoder_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_encoder_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module encoder_using_if ( binary_out, encoder_in, enable); output [3:0] binary_out; input enable; input [15:0] encoder_in; reg [3:0] binary_out; always @(enable or encoder_in) begin binary_out = 0; if (enable) begin if ((encoder_in == 16'h0002)) begin binary_out = 1; end if ((encoder_in == 16'h0004)) begin binary_out = 2; end if ((encoder_in == 16'h0008)) begin binary_out = 3; end if ((encoder_in == 16'h0010)) begin binary_out = 4; end if ((encoder_in == 16'h0020)) begin binary_out = 5; end if ((encoder_in == 16'h0040)) begin binary_out = 6; end if ((encoder_in == 16'h0080)) begin binary_out = 7; end if ((encoder_in == 16'h0100)) begin binary_out = 8; end if ((encoder_in == 16'h0200)) begin binary_out = 9; end if ((encoder_in == 16'h0400)) begin binary_out = 10; end if ((encoder_in == 16'h0800)) begin binary_out = 11; end if ((encoder_in == 16'h1000)) begin binary_out = 12; end if ((encoder_in == 16'h2000)) begin binary_out = 13; end if ((encoder_in == 16'h4000)) begin binary_out = 14; end if ((encoder_in == 16'h8000)) begin binary_out = 15; end end endendmodule
name: simple_vloghammerdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/vloghammer.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module test01 ( a, y); input [7:0] a; output [3:0] y; assign y = ((~ a) >> 4);endmodulemodule test02 ( a, y); input signed [3:0] a; output signed [4:0] y; assign y = ((~ a) >> 1);endmodulemodule test03 ( a, b, y); input [2:0] a; input signed [1:0] b; output y; assign y = ((~ (a >>> 1)) == b);endmodulemodule test04 ( a, y); input a; output [1:0] y; assign y = (~ (a - 1'b0));endmodulemodule test07 ( a, b, y); input signed [1:0] a; input signed [2:0] b; output y; assign y = (2'b11 != (a + b));endmodulemodule test08 ( a, b, y); input [1:0] a; input [1:0] b; output y; assign y = (a == ($signed(b) >>> 1));endmodulemodule test09 ( a, b, c, y); input a; input signed [1:0] b; input signed [2:0] c; output [3:0] y; assign y = (a ? b : c);endmodulemodule test10 ( a, b, c, y); input a; input signed [1:0] b; input signed [2:0] c; output y; assign y = (^ (a ? b : c));endmodule
name: asicworld_code_verilog_tutorial_simple_functiondescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_simple_function.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module simple_function; function myfunction; input reg a; input reg b; input reg c; input reg d; begin myfunction = ((a + b) + (c - d)); end endfunctionendmodule
name: svinterfaces_svinterface_at_topdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface_at_top.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1zachjs-sv2v: interface instantiations with parameter bindings are not yet supported: ("MyInterface",[("WIDTH",Right 4)],"MyInterfaceInstance")CallStack (from HasCallStack): error, called at src/Convert/Interface.hs:90:26 in main:Convert.Interface
name: asicworld_code_hdl_models_mux_using_ifdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_using_if.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module mux_using_if ( din_0, din_1, sel, mux_out); input din_0; input din_1; input sel; output mux_out; reg mux_out; always @(sel or din_0 or din_1) begin : MUX if ((sel == 1'b0)) begin mux_out = din_0; end else begin mux_out = din_1; end endendmodule
name: asicworld_code_hdl_models_mux_2to1_gatesdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_hdl_models_mux_2to1_gates.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module mux_2to1_gates ( a, b, sel, y); input a; input b; input sel; output y; wire sel; wire a_sel; wire b_sel; not U_inv (inv_sel, sel); and U_anda (asel, a, inv_sel); and U_andb (bsel, b, sel); or U_or (y, asel, bsel);endmodule
name: svinterfaces_svinterface1description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/svinterfaces/svinterface1.sv']should_fail: 0tags: yosysincdirs: []top_module: rc: 1zachjs-sv2v: interface instantiations with parameter bindings are not yet supported: ("MyInterface",[("WIDTH",Right 4)],"MyInterfaceInstance")CallStack (from HasCallStack): error, called at src/Convert/Interface.hs:90:26 in main:Convert.Interface
name: simple_constmuldivmoddescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/simple/constmuldivmod.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module constmuldivmod ( A, mode, Y); input [7:0] A; input [2:0] mode; output reg [7:0] Y; always @(*) begin case (mode) 0: Y = (A / 8'd0); 1: Y = (A % 8'd0); 2: Y = (A * 8'd0); 3: Y = (A / 8'd1); 4: Y = (A % 8'd1); 5: Y = (A * 8'd1); 6: Y = (A / 8'd2); 7: Y = (A % 8'd2); 8: Y = (A * 8'd2); 9: Y = (A / 8'd4); 10: Y = (A % 8'd4); 11: Y = (A * 8'd4); 12: Y = (A / 8'd8); 13: Y = (A % 8'd8); 14: Y = (A * 8'd8); default: Y = (8'd16 * A); endcase endendmodule
name: asicworld_code_verilog_tutorial_explicitdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_explicit.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module explicit; wire clk; wire d; wire rst; wire pre; wire q; dff u0( .q(q), .d(d), .clk(clk), .q_bar(), .rst(rst), .pre(pre) );endmodulemodule dff ( q, q_bar, clk, d, rst, pre); input clk; input d; input rst; input pre; output q; output q_bar; reg q; assign q_bar = (~ q); always @(posedge clk) if ((rst == 1'b1)) begin q <= 0; end else if ((pre == 1'b1)) begin q <= 1; end else begin q <= d; endendmodule
name: asicworld_code_verilog_tutorial_fsm_fulldescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_fsm_full.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module fsm_full ( clock, reset, req_0, req_1, req_2, req_3, gnt_0, gnt_1, gnt_2, gnt_3); input clock; input reset; input req_0; input req_1; input req_2; input req_3; output gnt_0; output gnt_1; output gnt_2; output gnt_3; reg gnt_0; reg gnt_1; reg gnt_2; reg gnt_3; parameter [2:0] IDLE = 3'b000; parameter [2:0] GNT0 = 3'b001; parameter [2:0] GNT1 = 3'b010; parameter [2:0] GNT2 = 3'b011; parameter [2:0] GNT3 = 3'b100; reg [2:0] state; reg [2:0] next_state; always @(state or req_0 or req_1 or req_2 or req_3) begin next_state = 0; case (state) IDLE: if ((req_0 == 1'b1)) begin next_state = GNT0; end else if ((req_1 == 1'b1)) begin next_state = GNT1; end else if ((req_2 == 1'b1)) begin next_state = GNT2; end else if ((req_3 == 1'b1)) begin next_state = GNT3; end else begin next_state = IDLE; end GNT0: if ((req_0 == 1'b0)) begin next_state = IDLE; end else begin next_state = GNT0; end GNT1: if ((req_1 == 1'b0)) begin next_state = IDLE; end else begin next_state = GNT1; end GNT2: if ((req_2 == 1'b0)) begin next_state = IDLE; end else begin next_state = GNT2; end GNT3: if ((req_3 == 1'b0)) begin next_state = IDLE; end else begin next_state = GNT3; end default: next_state = IDLE; endcase end always @(posedge clock) begin : OUTPUT_LOGIC if (reset) begin gnt_0 <= 1'b0; gnt_1 <= 1'b0; gnt_2 <= 1'b0; gnt_3 <= 1'b0; state <= IDLE; end else begin state <= next_state; case (state) IDLE: begin gnt_0 <= 1'b0; gnt_1 <= 1'b0; gnt_2 <= 1'b0; gnt_3 <= 1'b0; end GNT0: begin gnt_0 <= 1'b1; end GNT1: begin gnt_1 <= 1'b1; end GNT2: begin gnt_2 <= 1'b1; end GNT3: begin gnt_3 <= 1'b1; end default: begin state <= IDLE; end endcase end endendmodule
name: asicworld_code_verilog_tutorial_mux_21description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_mux_21.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module mux_21 ( a, b, sel, y); input a; input b; output y; input sel; wire y; assign y = (sel ? b : a);endmodule
name: asicworld_code_verilog_tutorial_v2k_regdescription: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/asicworld/code_verilog_tutorial_v2k_reg.v']should_fail: 0tags: yosysincdirs: []top_module: rc: 0module v2k_reg; wire a = 0; wire b; wire c; wire d = 0; wire signed [7:0] data = 8'shF0; function signed [7:0] adder; input reg a_in; input reg b_in; input reg c_in; input reg signed [7:0] data_in; begin adder = (((a_in + b_in) + c_in) + data_in); end endfunctionendmodule
name: errors_syntax_err06description: Tests imported from yosysfiles: ['/home/travis/build/SymbiFlow/sv-tests/third_party/tools/yosys/tests/errors/syntax_err06.v']should_fail: 1tags: yosysincdirs: []top_module: rc: 1zachjs-sv2v: tag mismatch: ("label1","label2")CallStack (from HasCallStack): error, called at .stack-work/dist/x86_64-linux/Cabal-2.4.0.1/build/sv2v/sv2v-tmp/Language/SystemVerilog/Parser/Parse.hs:7079:10 in main:Language.SystemVerilog.Parser.Parse
name: string-basicdescription: Basic string exampleshould_fail: 0tags: 5.9 5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: empty_test_2description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_1description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_3description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_0description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_4description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_5description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: commentsdescription: A module testing system verilog commentsshould_fail: 0tags: 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv::15 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_2description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_1description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_3description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_0description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_4description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: empty_test_5description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: commentsdescription: A module testing system verilog commentsshould_fail: 0tags: 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv']incdirs: []top_module: rc: 0
name: empty_test_2description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_2.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: empty_test_1description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_1.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: empty_test_3description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_3.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: empty_test_0description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_0.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: empty_test_4description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_4.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: empty_test_5description: Testshould_fail: 0tags: 5.3 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/empty/empty_test_5.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: commentsdescription: A module testing system verilog commentsshould_fail: 0tags: 5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.4--coments.sv']incdirs: []top_module: rc: 0module empty; endmodule
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8:6: error: expected declarator reg $dollar; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8:7: error: expected member reg $dollar; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9:6: error: expected declarator reg 0number; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9:7: error: expected member reg 0number; ^
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 1(0, 0) source_file(6, 0) module_declaration(7, 2) ERROR(8, 2) module_or_generate_item(8, 2) data_declaration(8, 6) ERROR
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8: Unsupported or unknown PLI call: $dollar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8: syntax error, unexpected ${ignored-bbox-sys}, expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9: syntax error, unexpected TOK_CONST
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv' to AST representation.Generating RTLIL representation for module `\identifiers'.Successfully finished Verilog frontend.
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv::8 error in parsing: (syntax error, unexpected vCFUNC, expecting vSYMBOL_ID or vSIGNED or '[') reg $dollar;
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:8: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9: error: invalid module item.
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0
name: wrong-identifiersdescription: Identifiers that should not be acceptedshould_fail: 1tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--wrong-identifiers.sv:9:7: Parse error: unexpected token '0' (Lit_number).
name: identifiersdescription: Identifiers that should be acceptedshould_fail: 0tags: 5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6--identifiers.sv']incdirs: []top_module: rc: 0module identifiers; wire shiftreg_a; wire busa_index; wire error_condition; wire merge_ab; wire _bus3; wire n$657; wire sensitive; wire Sensitive;endmodule
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: 0
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: 0
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: 0
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv' to AST representation.Generating RTLIL representation for module `\identifiers'.Successfully finished Verilog frontend.
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv::9 error in parsing: (syntax error, unexpected '+', expecting ';' or ',') reg \busa+index ;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv::12 error in parsing: (syntax error, unexpected '/', expecting ';' or ',') reg \net1/\net2 ;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv::14 error in parsing: (syntax error, unexpected '*', expecting ';' or ',') reg \a*(b+c) ;
name: escaped-identifiersdescription: Escaped identifiers that should be acceptedshould_fail: 0tags: 5.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.1--escaped-identifiers.sv']incdirs: []top_module: rc: 0
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8:8: error: expected declarator bit extends; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8:9: error: expected member bit extends; ^~~~~~~
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv:8:8: error: expected declarator bit uwire; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv:8:14: error: expected declarator bit uwire; ^
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:8: error: expected declarator bit cover; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:9: error: language feature not yet supported bit cover; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:14: error: expected expression bit cover; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:14: error: expected '(' bit cover; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:14: error: expected ')' bit cover; ^
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8:8: error: expected declarator bit tranif0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8:9: error: expected member bit tranif0; ^~~~~~~
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8:8: error: expected declarator bit casex; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8:9: error: expected member bit casex; ^~~~~
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8:8: error: expected declarator bit coverpoint; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8:9: error: expected member bit coverpoint; ^~~~~~~~~~
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8:8: error: expected declarator bit until; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8:9: error: expected member bit until; ^~~~~
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8:8: error: expected declarator bit endpackage; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8:9: error: expected member bit endpackage; ^~~~~~~~~~
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8:8: error: expected declarator bit program; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8:16: error: expected identifier bit program; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:9:10: error: expected 'endprogram'endmodule ^
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8:8: error: expected declarator bit do; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8:9: error: expected member bit do; ^~
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8:8: error: expected declarator bit endprimitive; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8:9: error: expected member bit endprimitive; ^~~~~~~~~~~~
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8:8: error: expected declarator bit sequence; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8:9: error: language feature not yet supported bit sequence; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8:17: error: expected identifier bit sequence; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8:18: error: expected ';' bit sequence; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:9:1: error: expected expressionendmodule^
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8:8: error: expected declarator bit join_any; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8:9: error: expected member bit join_any; ^~~~~~~~
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8:8: error: expected declarator bit s_nexttime; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8:9: error: expected member bit s_nexttime; ^~~~~~~~~~
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8:8: error: expected declarator bit nor; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8:9: error: expected member bit nor; ^~~
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8:8: error: expected declarator bit genvar; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8:15: error: expected identifier bit genvar; ^
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8:8: error: expected declarator bit ref; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8:9: error: can't use port declaration in module with ANSI style port list bit ref; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8:12: error: expected declarator bit ref; ^
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8:8: error: expected declarator bit incdir; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8:9: error: expected member bit incdir; ^~~~~~
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8:8: error: expected declarator bit nand; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8:9: error: expected member bit nand; ^~~~
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8:8: error: expected declarator bit or; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8:9: error: expected member bit or; ^~
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8:8: error: expected declarator bit nmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8:9: error: expected member bit nmos; ^~~~
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8:8: error: expected declarator bit wait_order; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8:9: error: expected member bit wait_order; ^~~~~~~~~~
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8:8: error: expected declarator bit weak; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8:9: error: expected member bit weak; ^~~~
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 3internal compiler error: /home/travis/build/SymbiFlow/sv-tests/third_party/tools/slang/source/parsing/Parser_statements.cpp:464: Default case should be unreachable!
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8:8: error: expected declarator bit package; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8:16: error: expected identifier bit package; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:9:10: error: expected 'endpackage'endmodule ^
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8:8: error: expected declarator bit cross; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8:9: error: expected member bit cross; ^~~~~
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8:8: error: expected declarator bit pull0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8:9: error: expected member bit pull0; ^~~~~
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8:8: error: expected declarator bit endsequence; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8:9: error: expected member bit endsequence; ^~~~~~~~~~~
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8:8: error: expected declarator bit solve; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8:9: error: expected member bit solve; ^~~~~
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8:8: error: expected declarator bit covergroup; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8:9: error: language feature not yet supported bit covergroup; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8:19: error: expected identifier bit covergroup; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:9:10: error: expected 'endgroup'endmodule ^
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8:8: error: expected declarator bit void; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8:9: error: expected member bit void; ^~~~
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8:8: error: expected declarator bit endclocking; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8:9: error: expected member bit endclocking; ^~~~~~~~~~~
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8:8: error: expected declarator bit endfunction; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8:9: error: expected member bit endfunction; ^~~~~~~~~~~
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8:8: error: expected declarator bit extern; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8:9: error: expected member bit extern; ^~~~~~
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8:8: error: expected declarator bit nettype; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8:16: error: expected identifier bit nettype; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8:16: error: expected data type (implicit type name not allowed) bit nettype; ^
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv:8:15: error: expected declarator bit signed; ^
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8:8: error: expected declarator bit string; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8:15: error: expected declarator bit string; ^
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8:8: error: expected declarator bit super; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8:9: error: expected member bit super; ^~~~~
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8:8: error: expected declarator bit while; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8:9: error: expected member bit while; ^~~~~
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8:8: error: expected declarator bit negedge; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8:9: error: expected member bit negedge; ^~~~~~~
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8:8: error: expected declarator bit bit; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8:12: error: expected declarator bit bit; ^
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8:8: error: expected declarator bit function; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8:17: error: expected identifier bit function; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8:18: error: expected 'endfunction' bit function; ^
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8:8: error: expected declarator bit pulsestyle_ondetect; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8:9: error: expected member bit pulsestyle_ondetect; ^~~~~~~~~~~~~~~~~~~
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8:8: error: expected declarator bit chandle; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8:16: error: expected declarator bit chandle; ^
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8:8: error: expected declarator bit inside; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8:9: error: expected member bit inside; ^~~~~~
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8:8: error: expected declarator bit config; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8:9: error: expected member bit config; ^~~~~~
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8:8: error: expected declarator bit library; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8:9: error: expected member bit library; ^~~~~~~
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8:8: error: expected declarator bit shortreal; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8:18: error: expected declarator bit shortreal; ^
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8:8: error: expected declarator bit generate; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:9:10: error: expected 'endgenerate'endmodule ^
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8:8: error: expected declarator bit const; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8:14: error: expected data type (implicit type name not allowed) bit const; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8:14: error: expected declarator bit const; ^
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8:8: error: expected declarator bit buf; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8:9: error: expected member bit buf; ^~~
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8:8: error: expected declarator bit use; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8:9: error: expected member bit use; ^~~
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8:8: error: expected declarator bit instance; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8:9: error: expected member bit instance; ^~~~~~~~
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8:8: error: expected declarator bit include; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8:9: error: expected member bit include; ^~~~~~~
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8:8: error: expected declarator bit endgroup; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8:9: error: expected member bit endgroup; ^~~~~~~~
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8:8: error: expected declarator bit enum; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8:13: error: expected '{' bit enum; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8:13: error: expected data type (implicit type name not allowed) bit enum; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8:13: error: expected declarator bit enum; ^
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8:8: error: expected declarator bit soft; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8:9: error: expected member bit soft; ^~~~
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8:8: error: expected declarator bit endcase; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8:9: error: expected member bit endcase; ^~~~~~~
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8:8: error: expected declarator bit accept_on; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8:9: error: expected member bit accept_on; ^~~~~~~~~
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8:8: error: expected declarator bit event; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8:14: error: expected declarator bit event; ^
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8:8: error: expected declarator bit sync_accept_on; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8:9: error: expected member bit sync_accept_on; ^~~~~~~~~~~~~~
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8:8: error: expected declarator bit binsof; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8:9: error: expected member bit binsof; ^~~~~~
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8:8: error: expected declarator bit new; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8:9: error: expected member bit new; ^~~
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8:8: error: expected declarator bit pmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8:9: error: expected member bit pmos; ^~~~
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8:8: error: expected declarator bit pullup; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8:9: error: expected member bit pullup; ^~~~~~
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8:8: error: expected declarator bit unique; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8:9: error: expected member bit unique; ^~~~~~
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8:8: error: expected declarator bit wire; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8:13: error: expected declarator bit wire; ^
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8:8: error: expected declarator bit always_comb; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8:20: error: expected statement bit always_comb; ^
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8:8: error: expected declarator bit trireg; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8:15: error: expected declarator bit trireg; ^
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8:8: error: expected declarator bit cmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8:9: error: expected member bit cmos; ^~~~
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8:8: error: expected declarator bit endgenerate; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8:9: error: expected member bit endgenerate; ^~~~~~~~~~~
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8:8: error: expected declarator bit real; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8:13: error: expected declarator bit real; ^
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8:8: error: expected declarator bit weak0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8:9: error: expected member bit weak0; ^~~~~
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8:8: error: expected declarator bit always_ff; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8:18: error: expected statement bit always_ff; ^
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8:8: error: expected declarator bit strong; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8:9: error: expected member bit strong; ^~~~~~
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8:8: error: expected declarator bit rand; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8:9: error: expected member bit rand; ^~~~
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8:8: error: expected declarator bit reject_on; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8:9: error: expected member bit reject_on; ^~~~~~~~~
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8:8: error: expected declarator bit timeunit; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8:17: error: expected time literal bit timeunit; ^
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8:8: error: expected declarator bit s_eventually; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8:9: error: expected member bit s_eventually; ^~~~~~~~~~~~
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8:8: error: expected declarator bit implies; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8:9: error: expected member bit implies; ^~~~~~~
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8:8: error: expected declarator bit bind; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8:9: error: expected member bit bind; ^~~~
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv:8:8: error: expected declarator bit shortint; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv:8:17: error: expected declarator bit shortint; ^
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8:8: error: expected declarator bit constraint; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8:9: error: expected member bit constraint; ^~~~~~~~~~
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8:8: error: expected declarator bit initial; ^
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8:8: error: expected declarator bit unique0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8:9: error: expected member bit unique0; ^~~~~~~
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8:8: error: expected declarator bit wait; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8:9: error: expected member bit wait; ^~~~
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8:8: error: expected declarator bit automatic; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8:18: error: expected data type (implicit type name not allowed) bit automatic; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8:18: error: expected declarator bit automatic; ^
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8:8: error: expected declarator bit wor; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8:12: error: expected declarator bit wor; ^
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8:8: error: expected declarator bit pure; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8:9: error: expected member bit pure; ^~~~
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:8: error: expected declarator bit assume; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:9: error: language feature not yet supported bit assume; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:15: error: expected expression bit assume; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:15: error: expected '(' bit assume; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:15: error: expected ')' bit assume; ^
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8:8: error: expected declarator bit interface; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8:18: error: expected identifier bit interface; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:9:10: error: expected 'endinterface'endmodule ^
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8:8: error: expected declarator bit strong1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8:9: error: expected member bit strong1; ^~~~~~~
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8:8: error: expected declarator bit macromodule; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8:20: error: expected identifier bit macromodule; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:9:10: error: expected 'endmodule'endmodule ^
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8:8: error: expected declarator bit endmodule; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:9:1: error: expected memberendmodule^~~~~~~~~
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:8: error: expected declarator bit case; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:9: error: case generate has no items bit case; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:13: error: expected expression bit case; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:13: error: expected '(' bit case; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:13: error: expected ')' bit case; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:13: error: expected 'endcase' bit case; ^
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8:8: error: expected declarator bit notif0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8:9: error: expected member bit notif0; ^~~~~~
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8:8: error: expected declarator bit strong0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8:9: error: expected member bit strong0; ^~~~~~~
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8:8: error: expected declarator bit rpmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8:9: error: expected member bit rpmos; ^~~~~
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8:8: error: expected declarator bit module; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8:15: error: expected identifier bit module; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:9:10: error: expected 'endmodule'endmodule ^
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8:8: error: expected declarator bit design; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8:9: error: expected member bit design; ^~~~~~
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8:8: error: expected declarator bit specify; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8:9: error: expected member bit specify; ^~~~~~~
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8:8: error: expected declarator bit repeat; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8:9: error: expected member bit repeat; ^~~~~~
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv:8:8: error: expected declarator bit realtime; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv:8:17: error: expected declarator bit realtime; ^
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv:8:17: error: expected declarator bit unsigned; ^
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8:8: error: expected declarator bit task; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8:13: error: expected identifier bit task; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8:14: error: expected 'endtask' bit task; ^
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8:8: error: expected declarator bit import; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8:15: error: expected package import bit import; ^
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8:8: error: expected declarator bit always; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8:15: error: expected statement bit always; ^
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8:8: error: expected declarator bit pull1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8:9: error: expected member bit pull1; ^~~~~
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8:8: error: expected declarator bit this; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8:9: error: expected member bit this; ^~~~
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv:8:8: error: expected declarator bit time; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv:8:13: error: expected declarator bit time; ^
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8:8: error: expected declarator bit rtranif1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8:9: error: expected member bit rtranif1; ^~~~~~~~
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8:8: error: expected declarator bit first_match; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8:9: error: expected member bit first_match; ^~~~~~~~~~~
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8:8: error: expected declarator bit nexttime; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8:9: error: expected member bit nexttime; ^~~~~~~~
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8:8: error: expected declarator bit rtran; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8:9: error: expected member bit rtran; ^~~~~
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8:8: error: expected declarator bit throughout; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8:9: error: expected member bit throughout; ^~~~~~~~~~
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8:8: error: expected declarator bit foreach; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8:9: error: expected member bit foreach; ^~~~~~~
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:8: error: expected declarator bit for; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:12: error: expected expression bit for; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:12: error: expected '(' bit for; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:13: error: expected ';' bit for; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:13: error: expected ')' bit for; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:9:1: error: expected expressionendmodule^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:9:1: error: expected expressionendmodule^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:9:1: error: invalid genvar iteration expressionendmodule^
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8:8: error: expected declarator bit not; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8:9: error: expected member bit not; ^~~
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8:8: error: expected declarator bit large; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8:9: error: expected member bit large; ^~~~~
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8:8: error: expected declarator bit endclass; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8:9: error: expected member bit endclass; ^~~~~~~~
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8:8: error: expected declarator bit s_always; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8:9: error: expected member bit s_always; ^~~~~~~~
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8:8: error: expected declarator bit specparam; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8:9: error: expected member bit specparam; ^~~~~~~~~
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8:8: error: expected declarator bit and; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8:9: error: expected member bit and; ^~~
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8:8: error: expected declarator bit null; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8:9: error: expected member bit null; ^~~~
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8:8: error: expected declarator bit forever; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8:9: error: expected member bit forever; ^~~~~~~
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8:8: error: expected declarator bit cell; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8:9: error: expected member bit cell; ^~~~
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8:8: error: expected declarator bit parameter; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8:18: error: expected declarator bit parameter; ^
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8:8: error: expected declarator bit bins; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8:9: error: expected member bit bins; ^~~~
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8:8: error: expected declarator bit join_none; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8:9: error: expected member bit join_none; ^~~~~~~~~
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8:8: error: expected declarator bit clocking; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8:9: error: language feature not yet supported bit clocking; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8:17: error: expected identifier bit clocking; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8:18: error: expected 'endclocking' bit clocking; ^
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8:8: error: expected declarator bit timeprecision; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8:22: error: expected time literal bit timeprecision; ^
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8:8: error: expected declarator bit with; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8:9: error: expected member bit with; ^~~~
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8:8: error: expected declarator bit randc; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8:9: error: expected member bit randc; ^~~~~
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8:8: error: expected declarator bit class; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8:9: error: language feature not yet supported bit class; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8:14: error: expected identifier bit class; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:9:10: error: expected 'endclass'endmodule ^
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8:8: error: expected declarator bit intersect; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8:9: error: expected member bit intersect; ^~~~~~~~~
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8:8: error: expected declarator bit defparam; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8:9: error: language feature not yet supported bit defparam; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8:17: error: expected variable assignment bit defparam; ^
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8:8: error: expected declarator bit dist; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8:9: error: expected member bit dist; ^~~~
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8:8: error: expected declarator bit protected; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8:9: error: expected member bit protected; ^~~~~~~~~
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:8: error: expected declarator bit assert; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:9: error: language feature not yet supported bit assert; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:15: error: expected expression bit assert; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:15: error: expected '(' bit assert; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:15: error: expected ')' bit assert; ^
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8:8: error: expected declarator bit xnor; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8:9: error: expected member bit xnor; ^~~~
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8:8: error: expected declarator bit disable; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8:9: error: expected member bit disable; ^~~~~~~
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8:8: error: expected declarator bit tran; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8:9: error: expected member bit tran; ^~~~
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8:8: error: expected declarator bit typedef; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8:16: error: expected identifier bit typedef; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8:16: error: expected data type (implicit type name not allowed) bit typedef; ^
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8:8: error: expected declarator bit weak1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8:9: error: expected member bit weak1; ^~~~~
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8:8: error: expected declarator bit showcancelled; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8:9: error: expected member bit showcancelled; ^~~~~~~~~~~~~
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8:8: error: expected declarator bit ignore_bins; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8:9: error: expected member bit ignore_bins; ^~~~~~~~~~~
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8:8: error: expected declarator bit table; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8:9: error: expected member bit table; ^~~~~
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8:8: error: expected declarator bit rcmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8:9: error: expected member bit rcmos; ^~~~~
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8:8: error: expected declarator bit output; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8:9: error: can't use port declaration in module with ANSI style port list bit output; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8:15: error: expected declarator bit output; ^
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8:8: error: expected declarator bit fork; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8:9: error: expected member bit fork; ^~~~
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8:8: error: expected declarator bit input; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8:9: error: can't use port declaration in module with ANSI style port list bit input; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8:14: error: expected declarator bit input; ^
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8:8: error: expected declarator bit rtranif0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8:9: error: expected member bit rtranif0; ^~~~~~~~
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8:8: error: expected declarator bit packed; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8:9: error: expected member bit packed; ^~~~~~
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8:8: error: expected declarator bit priority; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8:9: error: expected member bit priority; ^~~~~~~~
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8:8: error: expected declarator bit expect; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8:9: error: expected member bit expect; ^~~~~~
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8:8: error: expected declarator bit break; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8:9: error: expected member bit break; ^~~~~
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv:8:8: error: expected declarator bit global; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv:8:9: error: expected member bit global; ^~~~~~
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8:8: error: expected declarator bit property; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8:9: error: language feature not yet supported bit property; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8:17: error: expected identifier bit property; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8:18: error: expected 'endproperty' bit property; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:9:1: error: expected expressionendmodule^
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8:8: error: expected declarator bit s_until_with; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8:9: error: expected member bit s_until_with; ^~~~~~~~~~~~
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8:8: error: expected declarator bit bufif0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8:9: error: expected member bit bufif0; ^~~~~~
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8:8: error: expected declarator bit implements; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8:9: error: expected member bit implements; ^~~~~~~~~~
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8:8: error: expected declarator bit tranif1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8:9: error: expected member bit tranif1; ^~~~~~~
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8:8: error: expected declarator bit bufif1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8:9: error: expected member bit bufif1; ^~~~~~
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8:8: error: expected declarator bit highz1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8:9: error: expected member bit highz1; ^~~~~~
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8:8: error: expected declarator bit before; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8:9: error: expected member bit before; ^~~~~~
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8:8: error: expected declarator bit union; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8:14: error: expected '{' bit union; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8:14: error: expected declarator bit union; ^
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8:8: error: expected declarator bit static; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8:15: error: expected data type (implicit type name not allowed) bit static; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8:15: error: expected declarator bit static; ^
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8:8: error: expected declarator bit final; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8:14: error: expected statement bit final; ^
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8:8: error: expected declarator bit until_with; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8:9: error: expected member bit until_with; ^~~~~~~~~~
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8:8: error: expected declarator bit checker; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8:9: error: expected member bit checker; ^~~~~~~
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8:8: error: expected declarator bit endchecker; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8:9: error: expected member bit endchecker; ^~~~~~~~~~
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8:8: error: expected declarator bit localparam; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8:19: error: expected declarator bit localparam; ^
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8:8: error: expected declarator bit type; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8:9: error: expected member bit type; ^~~~
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8:8: error: expected declarator bit edge; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8:9: error: expected member bit edge; ^~~~
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8:8: error: expected declarator bit s_until; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8:9: error: expected member bit s_until; ^~~~~~~
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8:8: error: expected declarator bit untyped; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8:9: error: expected member bit untyped; ^~~~~~~
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8:8: error: expected declarator bit integer; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8:16: error: expected declarator bit integer; ^
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8:8: error: expected declarator bit eventually; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8:9: error: expected member bit eventually; ^~~~~~~~~~
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8:8: error: expected declarator bit xor; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8:9: error: expected member bit xor; ^~~
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8:8: error: expected declarator bit local; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8:9: error: expected member bit local; ^~~~~
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8:8: error: expected declarator bit noshowcancelled; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8:9: error: expected member bit noshowcancelled; ^~~~~~~~~~~~~~~
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8:8: error: expected declarator bit if; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8:11: error: expected expression bit if; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8:11: error: expected '(' bit if; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8:11: error: expected ')' bit if; ^
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8:8: error: expected declarator bit medium; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8:9: error: expected member bit medium; ^~~~~~
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8:8: error: expected declarator bit wand; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8:13: error: expected declarator bit wand; ^
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8:8: error: expected declarator bit illegal_bins; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8:9: error: expected member bit illegal_bins; ^~~~~~~~~~~~
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8:8: error: expected declarator bit always_latch; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8:21: error: expected statement bit always_latch; ^
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8:8: error: expected declarator bit rnmos; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8:9: error: expected member bit rnmos; ^~~~~
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8:8: error: expected declarator bit export; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8:9: error: language feature not yet supported bit export; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8:15: error: expected string literal bit export; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8:15: error: expected 'function' bit export; ^
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8:8: error: expected declarator bit var; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8:12: error: expected declarator bit var; ^
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8:8: error: expected declarator bit liblist; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8:9: error: expected member bit liblist; ^~~~~~~
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv:8:8: error: expected declarator bit tri; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv:8:12: error: expected declarator bit tri; ^
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8:8: error: expected declarator bit release; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8:9: error: expected member bit release; ^~~~~~~
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8:8: error: expected declarator bit logic; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8:14: error: expected declarator bit logic; ^
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv:8:8: error: expected declarator bit tri1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv:8:13: error: expected declarator bit tri1; ^
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8:8: error: expected declarator bit notif1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8:9: error: expected member bit notif1; ^~~~~~
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8:8: error: expected declarator bit randsequence; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8:9: error: expected member bit randsequence; ^~~~~~~~~~~~
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8:8: error: expected declarator bit end; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8:9: error: expected member bit end; ^~~
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8:8: error: expected declarator bit join; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8:9: error: expected member bit join; ^~~~
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8:8: error: expected declarator bit inout; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8:9: error: can't use port declaration in module with ANSI style port list bit inout; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8:14: error: expected declarator bit inout; ^
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8:8: error: expected declarator bit scalared; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8:9: error: expected member bit scalared; ^~~~~~~~
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8:8: error: expected declarator bit virtual; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8:9: error: language feature not yet supported bit virtual; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8:17: error: expected identifier bit virtual; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:9:1: error: expected memberendmodule^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:9:10: error: expected 'endclass'endmodule ^
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv:8:8: error: expected declarator bit int; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv:8:12: error: expected declarator bit int; ^
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv:8:8: error: expected declarator bit longint; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv:8:16: error: expected declarator bit longint; ^
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8:8: error: expected declarator bit matches; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8:9: error: expected member bit matches; ^~~~~~~
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8:8: error: expected declarator bit assign; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8:15: error: expected variable assignment bit assign; ^
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8:8: error: expected declarator bit endspecify; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8:9: error: expected member bit endspecify; ^~~~~~~~~~
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8:8: error: expected declarator bit endproperty; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8:9: error: expected member bit endproperty; ^~~~~~~~~~~
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8:8: error: expected declarator bit wildcard; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8:9: error: expected member bit wildcard; ^~~~~~~~
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8:8: error: expected declarator bit sync_reject_on; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8:9: error: expected member bit sync_reject_on; ^~~~~~~~~~~~~~
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv:8:8: error: expected declarator bit tri0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv:8:13: error: expected declarator bit tri0; ^
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv:8:8: error: expected declarator bit byte; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv:8:13: error: expected declarator bit byte; ^
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8:8: error: expected declarator bit endtable; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8:9: error: expected member bit endtable; ^~~~~~~~
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8:8: error: expected declarator bit posedge; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8:9: error: expected member bit posedge; ^~~~~~~
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8:8: error: expected declarator bit supply0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8:16: error: expected declarator bit supply0; ^
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8:8: error: expected declarator bit interconnect; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8:9: error: expected member bit interconnect; ^~~~~~~~~~~~
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8:8: error: expected declarator bit casez; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8:9: error: expected member bit casez; ^~~~~
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:8: error: expected declarator bit let; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:9: error: language feature not yet supported bit let; ^~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:12: error: expected identifier bit let; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:12: error: expected expression bit let; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:12: error: expected '=' bit let; ^
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8:8: error: expected declarator bit pulldown; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8:9: error: expected member bit pulldown; ^~~~~~~~
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8:8: error: expected declarator bit alias; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8:9: error: expected member bit alias; ^~~~~
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8:8: error: expected declarator bit supply1; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8:16: error: expected declarator bit supply1; ^
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8:8: error: expected declarator bit highz0; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8:9: error: expected member bit highz0; ^~~~~~
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8:8: error: expected declarator bit ifnone; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8:9: error: expected member bit ifnone; ^~~~~~
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8:8: error: expected declarator bit begin; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8:9: error: expected member bit begin; ^~~~~
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8:8: error: expected declarator bit force; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8:9: error: expected member bit force; ^~~~~
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8:8: error: expected declarator bit vectored; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8:9: error: expected member bit vectored; ^~~~~~~~
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8:8: error: expected declarator bit context; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8:9: error: expected member bit context; ^~~~~~~
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8:8: error: expected declarator bit modport; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8:16: error: expected identifier bit modport; ^
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8:8: error: expected declarator bit default; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8:9: error: expected member bit default; ^~~~~~~
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8:8: error: expected declarator bit endtask; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8:9: error: expected member bit endtask; ^~~~~~~
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8:8: error: expected declarator bit within; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8:9: error: expected member bit within; ^~~~~~
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8:8: error: expected declarator bit forkjoin; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8:9: error: expected member bit forkjoin; ^~~~~~~~
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8:8: error: expected declarator bit primitive; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8:9: error: expected member bit primitive; ^~~~~~~~~
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8:8: error: expected declarator bit randcase; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8:9: error: expected member bit randcase; ^~~~~~~~
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8:8: error: expected declarator bit tagged; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8:9: error: expected member bit tagged; ^~~~~~
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8:8: error: expected declarator bit continue; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8:9: error: expected member bit continue; ^~~~~~~~
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8:8: error: expected declarator bit deassign; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8:9: error: expected member bit deassign; ^~~~~~~~
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8:8: error: expected declarator bit triand; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8:15: error: expected declarator bit triand; ^
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8:8: error: expected declarator bit struct; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8:15: error: expected '{' bit struct; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8:15: error: expected declarator bit struct; ^
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8:8: error: expected declarator bit pulsestyle_onevent; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8:9: error: expected member bit pulsestyle_onevent; ^~~~~~~~~~~~~~~~~~
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8:8: error: expected declarator bit return; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8:9: error: expected member bit return; ^~~~~~
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8:8: error: expected declarator bit small; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8:9: error: expected member bit small; ^~~~~
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8:8: error: expected declarator bit iff; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8:9: error: expected member bit iff; ^~~
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8:8: error: expected declarator bit else; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8:9: error: expected member bit else; ^~~~
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8:8: error: expected declarator bit trior; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8:14: error: expected declarator bit trior; ^
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8:8: error: expected declarator bit endconfig; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8:9: error: expected member bit endconfig; ^~~~~~~~~
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8:8: error: expected declarator bit reg; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8:12: error: expected declarator bit reg; ^
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8:8: error: expected declarator bit endinterface; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8:9: error: expected member bit endinterface; ^~~~~~~~~~~~
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8:8: error: expected declarator bit endprogram; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8:9: error: expected member bit endprogram; ^~~~~~~~~~
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 0
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 0
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 0
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 0
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 0
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 0
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 0
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 0
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 0
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 0
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 0
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 0
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 0
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 0
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 0
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 0
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 0
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 0
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 0
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 0
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 0
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 0
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 0
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 0
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 0
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 0
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 0
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 0
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 0
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 0
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 0
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 0
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 0
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 0
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 0
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 1(0, 0) source_file(6, 0) module_declaration(7, 4) ERROR
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 0
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 0
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 0
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 0
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 0
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 0
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 0
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 0
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 0
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 0
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 0
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 0
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 0
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 0
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 0
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 0
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 0
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 0
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 0
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 0
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 0
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 0
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 0
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 0
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 0
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 0
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 0
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 0
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 0
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 0
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 0
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 0
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 0
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 0
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 0
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 0
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 0
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 0
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 0
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 0
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 0
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 0
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 0
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 0
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 0
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 0
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 0
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 0
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 0
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 0
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 0
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 0
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 0
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 0
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 0
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 0
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 0
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 0
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 0
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 0
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 0
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 0
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 0
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 0
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 0
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 0
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 0
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 1(0, 0) source_file(6, 0) module_declaration(7, 4) module_or_generate_item(7, 4) data_declaration(7, 16) list_of_variable_decl_assignments(7, 16) variable_decl_assignment(7, 16) variable_identifier(7, 16) simple_identifier
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 0
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 0
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 0
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 0
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 0
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 0
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 0
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 0
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 0
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 0
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 0
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 0
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 0
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 0
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 0
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 0
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 0
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 0
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 0
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 0
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 0
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 0
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 0
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 0
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 0
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 0
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 0
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 0
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 0
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 0
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 0
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 0
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 0
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 0
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 0
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 0
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 0
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 0
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 0
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 0
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 0
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 0
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 0
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 0
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 0
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 0
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 0
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 0
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 0
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 0
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 0
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 0
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 0
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 0
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 0
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 0
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 0
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 0
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 0
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 0
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 0
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 0
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 0
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 0
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 0
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 0
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 0
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 0
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 0
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 0
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 0
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 0
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 0
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 0
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 0
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 0
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 0
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 0
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 0
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 0
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 0
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 0
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 0
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 0
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 0
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 0
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 0
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 0
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 0
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 0
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 0
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 0
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 0
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 0
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 0
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 0
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 0
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 0
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 0
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 0
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 0
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 0
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 0
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 0
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 0
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 0
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 0
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 0
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 0
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 0
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 0
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 0
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 0
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 0
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 0
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 0
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 0
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 0
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 0
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 0
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 0
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 0
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 0
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 0
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 0
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 0
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 0
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 0
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 0
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 0
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 0
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 0
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 0
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 0
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 0
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 0
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 0
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 0
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 0
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 0
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 0
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 0
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 0
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 0
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv:8: syntax error, unexpected wire, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8: syntax error, unexpected cover, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8: syntax error, unexpected tranif0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8: syntax error, unexpected casex, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: coverpoint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: until%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8: syntax error, unexpected endpackage, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8: syntax error, unexpected program, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8: Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8: syntax error, unexpected endprimitive, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: sequence%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: join_any%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: s_nexttime%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8: syntax error, unexpected nor, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8: syntax error, unexpected genvar, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: ref%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: incdir%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8: syntax error, unexpected nand, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8: syntax error, unexpected or, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8: syntax error, unexpected nmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: wait_order%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: weak%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: restrict%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8: syntax error, unexpected package, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: cross%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8: Unsupported: Verilog 1995 reserved word not implemented: pull0%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endsequence%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: solve%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: covergroup%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8: syntax error, unexpected void, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8: syntax error, unexpected endclocking, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8: syntax error, unexpected endfunction, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8: Unsupported: SystemVerilog 2012 reserved word not implemented: nettype%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8: syntax error, unexpected string, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8: syntax error, unexpected while, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8: syntax error, unexpected negedge, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8: syntax error, unexpected bit, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8: syntax error, unexpected function, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8: syntax error, unexpected TIMING SPEC ELEMENT, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8: syntax error, unexpected chandle, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8: syntax error, unexpected inside, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: config%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: library%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: shortreal%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8: syntax error, unexpected generate, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8: syntax error, unexpected const, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8: syntax error, unexpected buf, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: use%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: instance%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8: Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: include%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endgroup%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8: syntax error, unexpected enum, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8: Unsupported: SystemVerilog 2012 reserved word not implemented: soft%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8: syntax error, unexpected endcase, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: accept_on%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: sync_accept_on%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: binsof%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8: syntax error, unexpected pmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8: syntax error, unexpected pullup, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8: syntax error, unexpected unique, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8: syntax error, unexpected wire, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8: syntax error, unexpected always_comb, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8: Unsupported: Verilog 1995 reserved word not implemented: trireg%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8: syntax error, unexpected cmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8: syntax error, unexpected endgenerate, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8: syntax error, unexpected real, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8: Unsupported: Verilog 1995 reserved word not implemented: weak0%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8: syntax error, unexpected always_ff, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: strong%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8: syntax error, unexpected rand, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: reject_on%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8: syntax error, unexpected timeunit, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: s_eventually%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: implies%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8: syntax error, unexpected bind, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv:8: syntax error, unexpected shortint, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8: syntax error, unexpected initial, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8: syntax error, unexpected unique0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8: syntax error, unexpected automatic, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8: Unsupported: Verilog 1995 reserved word not implemented: wor%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8: syntax error, unexpected pure, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: assume%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8: syntax error, unexpected interface, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8: Unsupported: Verilog 1995 reserved word not implemented: strong1%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8: syntax error, unexpected module, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8: syntax error, unexpected endmodule, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8: syntax error, unexpected case, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8: syntax error, unexpected notif0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8: Unsupported: Verilog 1995 reserved word not implemented: strong0%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8: syntax error, unexpected rpmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8: syntax error, unexpected module, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: design%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8: syntax error, unexpected specify, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8: syntax error, unexpected repeat, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv:8: syntax error, unexpected realtime, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8: syntax error, unexpected task, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8: syntax error, unexpected import, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8: syntax error, unexpected always, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8: Unsupported: Verilog 1995 reserved word not implemented: pull1%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv:8: syntax error, unexpected time, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8: syntax error, unexpected rtranif1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: first_match%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: nexttime%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8: syntax error, unexpected rtran, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: throughout%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8: syntax error, unexpected foreach, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8: syntax error, unexpected for, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8: syntax error, unexpected not, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8: Unsupported: Verilog 1995 reserved word not implemented: large%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: s_always%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8: syntax error, unexpected specparam, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8: syntax error, unexpected and, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: null%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8: syntax error, unexpected forever, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: cell%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8: syntax error, unexpected parameter, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: bins%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8: syntax error, unexpected clocking, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8: syntax error, unexpected timeprecision, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8: syntax error, unexpected randc, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: intersect%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8: syntax error, unexpected defparam, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: dist%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8: syntax error, unexpected assert, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8: syntax error, unexpected xnor, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8: syntax error, unexpected disable, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8: syntax error, unexpected tran, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8: syntax error, unexpected typedef, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8: Unsupported: Verilog 1995 reserved word not implemented: weak1%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8: syntax error, unexpected TIMING SPEC ELEMENT, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: ignore_bins%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 2%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8: syntax error, unexpected table, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:11: EOF in TABLEfatal flex scanner internal error--end of buffer missed%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8: syntax error, unexpected rcmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8: syntax error, unexpected output, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8: syntax error, unexpected input, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8: syntax error, unexpected rtranif0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8: syntax error, unexpected packed, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8: syntax error, unexpected priority, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: expect%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8: syntax error, unexpected break, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 0
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8: syntax error, unexpected property, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: s_until_with%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8: syntax error, unexpected bufif0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8: syntax error, unexpected tranif1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8: syntax error, unexpected bufif1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8: Unsupported: Verilog 1995 reserved word not implemented: highz1%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: before%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8: syntax error, unexpected union, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8: syntax error, unexpected static, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8: Unexpected "final": "final" is a SystemVerilog keyword misused as an identifier.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8: Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: until_with%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: checker%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: endchecker%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8: syntax error, unexpected localparam, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8: syntax error, unexpected type, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8: syntax error, unexpected edge, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: s_until%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: untyped%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8: syntax error, unexpected integer, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: eventually%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8: syntax error, unexpected xor, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8: syntax error, unexpected TIMING SPEC ELEMENT, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8: syntax error, unexpected if, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8: Unsupported: Verilog 1995 reserved word not implemented: medium%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8: Unsupported: Verilog 1995 reserved word not implemented: wand%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: illegal_bins%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8: syntax error, unexpected always_latch, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8: syntax error, unexpected rnmos, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8: syntax error, unexpected export, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8: syntax error, unexpected var, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: liblist%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv:8: syntax error, unexpected tri, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8: Unsupported: Verilog 1995 reserved word not implemented: release%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8: syntax error, unexpected logic, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv:8: syntax error, unexpected tri1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8: syntax error, unexpected notif1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: randsequence%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8: syntax error, unexpected end, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8: Unsupported: Verilog 1995 reserved word not implemented: join%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8: syntax error, unexpected inout, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8: syntax error, unexpected scalared, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv:8: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv:8: syntax error, unexpected longint, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8: syntax error, unexpected assign, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8: syntax error, unexpected endspecify, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8: syntax error, unexpected endproperty, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: wildcard%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: sync_reject_on%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv:8: syntax error, unexpected tri0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv:8: syntax error, unexpected byte, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8: Syntax error: ENDTABLE outside of TABLE%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8: syntax error, unexpected posedge, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8: syntax error, unexpected supply0, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8: Unsupported: SystemVerilog 2012 reserved word not implemented: interconnect%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8: syntax error, unexpected casez, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8: Unsupported: SystemVerilog 2009 reserved word not implemented: let%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8: syntax error, unexpected pulldown, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: alias%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8: syntax error, unexpected supply1, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8: Unsupported: Verilog 1995 reserved word not implemented: highz0%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8: syntax error, unexpected TIMING SPEC ELEMENT, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8: syntax error, unexpected begin, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8: Unsupported: Verilog 1995 reserved word not implemented: force%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8: syntax error, unexpected vectored, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8: syntax error, unexpected context, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8: syntax error, unexpected modport, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8: syntax error, unexpected default, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8: syntax error, unexpected endtask, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: within%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: forkjoin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8: syntax error, unexpected primitive, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: randcase%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8: syntax error, unexpected continue, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8: syntax error, unexpected deassign, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8: Unsupported: Verilog 1995 reserved word not implemented: triand%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8: syntax error, unexpected struct, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8: syntax error, unexpected TIMING SPEC ELEMENT, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8: syntax error, unexpected return, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8: Unsupported: Verilog 1995 reserved word not implemented: small%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8: syntax error, unexpected iff, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8: syntax error, unexpected else, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8: Unsupported: Verilog 1995 reserved word not implemented: trior%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8: Unsupported: Verilog 2001-config reserved word not implemented: endconfig%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8: syntax error, unexpected reg, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8: syntax error, unexpected endinterface, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8: syntax error, unexpected endprogram, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8: syntax error, unexpected TOK_CASEX
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8: syntax error, unexpected TOK_ENDPACKAGE
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8: syntax error, unexpected ';'
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8: syntax error, unexpected TOK_OR
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8: syntax error, unexpected TOK_RESTRICT
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8: syntax error, unexpected TOK_PACKAGE
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8: syntax error, unexpected TOK_ENDFUNCTION
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv:8: syntax error, unexpected ';'
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8: syntax error, unexpected TOK_WHILE
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8: syntax error, unexpected TOK_NEGEDGE
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8: syntax error, unexpected ';'
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8: syntax error, unexpected TOK_FUNCTION
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8: syntax error, unexpected TOK_GENERATE
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8: syntax error, unexpected TOK_ENDCASE
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8: syntax error, unexpected ';'
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8: syntax error, unexpected TOK_ALWAYS
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8: syntax error, unexpected TOK_ENDGENERATE
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8: syntax error, unexpected TOK_REAL
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8: syntax error, unexpected TOK_ALWAYS
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8: syntax error, unexpected TOK_INITIAL
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8: syntax error, unexpected TOK_ASSUME
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8: syntax error, unexpected TOK_ENDMODULE
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8: syntax error, unexpected TOK_CASE
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8: syntax error, unexpected TOK_MODULE
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8: syntax error, unexpected TOK_REPEAT
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8: syntax error, unexpected TOK_TASK
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8: syntax error, unexpected TOK_ALWAYS
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8: syntax error, unexpected TOK_FOR
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8: syntax error, unexpected TOK_PARAMETER
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8: syntax error, unexpected TOK_DEFPARAM
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8: syntax error, unexpected TOK_ASSERT
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8: syntax error, unexpected ';'
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8: syntax error, unexpected ';'
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8: syntax error, unexpected TOK_PROPERTY
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8: syntax error, unexpected TOK_LOCALPARAM
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8: syntax error, unexpected ';'
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8: syntax error, unexpected TOK_IF
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8: syntax error, unexpected TOK_ALWAYS
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8: syntax error, unexpected ';'
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8: syntax error, unexpected TOK_PRIMITIVE
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8: syntax error, unexpected TOK_END
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8: syntax error, unexpected ';'
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8: syntax error, unexpected TOK_ASSIGN
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8: syntax error, unexpected TOK_POSEDGE
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8: syntax error, unexpected TOK_SUPPLY0
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8: syntax error, unexpected TOK_CASEZ
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8: syntax error, unexpected TOK_SUPPLY1
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8: syntax error, unexpected TOK_BEGIN
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8: syntax error, unexpected TOK_DEFAULT
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8: syntax error, unexpected TOK_ENDTASK
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8: syntax error, unexpected TOK_ELSE
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8: syntax error, unexpected ';'
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit extends;
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv::8 error in parsing: (syntax error, unexpected netUWIRE, expecting vSYMBOL_ID or '#') bit uwire;
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit cover;
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv::8 Unsuported token bit tranif0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit tranif0;
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv::8 Unsuported token bit casex; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit casex;
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit coverpoint;
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit until;
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endpackage;
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit program;
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit do;
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv::8 Unsuported token bit endprimitive; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit endprimitive;
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit sequence;
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit join_any;
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit s_nexttime;
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv::8 error in parsing: (syntax error, unexpected vNOR, expecting vSYMBOL_ID or '#') bit nor;
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv::8 error in parsing: (syntax error, unexpected vGENVAR, expecting vSYMBOL_ID or '#') bit genvar;
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit ref;
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit incdir;
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv::8 error in parsing: (syntax error, unexpected vNAND, expecting vSYMBOL_ID or '#') bit nand;
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv::8 error in parsing: (syntax error, unexpected vOR, expecting vSYMBOL_ID or '#') bit or;
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv::8 Unsuported token bit nmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit nmos;
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit wait_order;
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit weak;
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit restrict;
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit package;
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit cross;
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv::8 Unsuported token bit pull0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit pull0;
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endsequence;
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit solve;
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit covergroup;
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit void;
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endclocking;
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv::8 error in parsing: (syntax error, unexpected vENDFUNCTION, expecting vSYMBOL_ID or '#') bit endfunction;
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit extern;
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit nettype;
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv::8 error in parsing: (syntax error, unexpected vSIGNED, expecting vSYMBOL_ID or '#') bit signed;
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit string;
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit super;
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv::8 error in parsing: (syntax error, unexpected vWHILE, expecting vSYMBOL_ID or '#') bit while;
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv::8 error in parsing: (syntax error, unexpected vNEGEDGE, expecting vSYMBOL_ID or '#') bit negedge;
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit bit;
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv::8 error in parsing: (syntax error, unexpected vFUNCTION, expecting vSYMBOL_ID or '#') bit function;
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit pulsestyle_ondetect;
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit chandle;
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit inside;
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit config;
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit library;
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit shortreal;
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv::8 error in parsing: (syntax error, unexpected vGENERATE, expecting vSYMBOL_ID or '#') bit generate;
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit const;
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv::8 Unsuported token bit buf; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit buf;
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit use;
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit instance;
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit include;
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endgroup;
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit enum;
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit soft;
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv::8 error in parsing: (syntax error, unexpected vENDCASE, expecting vSYMBOL_ID or '#') bit endcase;
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit accept_on;
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv::8 Unsuported token bit event; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit event;
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit sync_accept_on;
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit binsof;
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit new;
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv::8 Unsuported token bit pmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit pmos;
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv::8 Unsuported token bit pullup; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit pullup;
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit unique;
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv::8 error in parsing: (syntax error, unexpected netWIRE, expecting vSYMBOL_ID or '#') bit wire;
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit always_comb;
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv::8 error in parsing: (syntax error, unexpected netTRIREG, expecting vSYMBOL_ID or '#') bit trireg;
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv::8 Unsuported token bit cmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit cmos;
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv::8 error in parsing: (syntax error, unexpected vENDGENERATE, expecting vSYMBOL_ID or '#') bit endgenerate;
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit real;
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv::8 Unsuported token bit weak0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit weak0;
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit always_ff;
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit strong;
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit rand;
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit reject_on;
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit timeunit;
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit s_eventually;
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit implies;
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit bind;
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit shortint;
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit constraint;
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv::8 error in parsing: (syntax error, unexpected vINITIAL, expecting vSYMBOL_ID or '#') bit initial;
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit unique0;
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv::8 Unsuported token bit wait; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit wait;
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv::8 error in parsing: (syntax error, unexpected vAUTOMATIC, expecting vSYMBOL_ID or '#') bit automatic;
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv::8 error in parsing: (syntax error, unexpected netWOR, expecting vSYMBOL_ID or '#') bit wor;
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit pure;
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit assume;
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit interface;
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv::8 Unsuported token bit strong1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit strong1;
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv::8 error in parsing: (syntax error, unexpected vMODULE, expecting vSYMBOL_ID or '#') bit macromodule;
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv::8 error in parsing: (syntax error, unexpected vENDMODULE, expecting vSYMBOL_ID or '#') bit endmodule;
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv::8 error in parsing: (syntax error, unexpected vCASE, expecting vSYMBOL_ID or '#') bit case;
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv::8 Unsuported token bit notif0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit notif0;
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv::8 Unsuported token bit strong0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit strong0;
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv::8 Unsuported token bit rpmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rpmos;
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv::8 error in parsing: (syntax error, unexpected vMODULE, expecting vSYMBOL_ID or '#') bit module;
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit design;
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv::8 error in parsing: (syntax error, unexpected vSPECIFY, expecting vSYMBOL_ID or '#') bit specify;
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv::8 Unsuported token bit repeat; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit repeat;
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit realtime;
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit unsigned;
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv::8 error in parsing: (syntax error, unexpected vTASK, expecting vSYMBOL_ID or '#') bit task;
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit import;
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv::8 error in parsing: (syntax error, unexpected vALWAYS, expecting vSYMBOL_ID or '#') bit always;
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv::8 Unsuported token bit pull1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit pull1;
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit this;
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv::8 Unsuported token bit time; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit time;
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv::8 Unsuported token bit rtranif1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rtranif1;
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit first_match;
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit nexttime;
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv::8 Unsuported token bit rtran; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rtran;
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit throughout;
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit foreach;
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv::8 error in parsing: (syntax error, unexpected vFOR, expecting vSYMBOL_ID or '#') bit for;
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv::8 error in parsing: (syntax error, unexpected vNOT, expecting vSYMBOL_ID or '#') bit not;
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv::8 Unsuported token bit large; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit large;
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endclass;
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit s_always;
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv::8 error in parsing: (syntax error, unexpected vSPECPARAM, expecting vSYMBOL_ID or '#') bit specparam;
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv::8 error in parsing: (syntax error, unexpected vAND, expecting vSYMBOL_ID or '#') bit and;
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit null;
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv::8 Unsuported token bit forever; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit forever;
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit cell;
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv::8 error in parsing: (syntax error, unexpected vPARAMETER, expecting vSYMBOL_ID or '#') bit parameter;
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit bins;
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit join_none;
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit clocking;
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit timeprecision;
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit with;
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit randc;
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit class;
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit intersect;
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv::8 error in parsing: (syntax error, unexpected vDEFPARAM, expecting vSYMBOL_ID or '#') bit defparam;
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit dist;
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit protected;
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit assert;
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv::8 error in parsing: (syntax error, unexpected vXNOR, expecting vSYMBOL_ID or '#') bit xnor;
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv::8 Unsuported token bit disable; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit disable;
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv::8 Unsuported token bit tran; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit tran;
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit typedef;
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv::8 Unsuported token bit weak1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit weak1;
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit showcancelled;
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit ignore_bins;
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv::8 Unsuported token bit table; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit table;
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv::8 Unsuported token bit rcmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rcmos;
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv::8 error in parsing: (syntax error, unexpected vOUTPUT, expecting vSYMBOL_ID or '#') bit output;
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv::8 Unsuported token bit fork; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit fork;
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv::8 error in parsing: (syntax error, unexpected vINPUT, expecting vSYMBOL_ID or '#') bit input;
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv::8 Unsuported token bit rtranif0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rtranif0;
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit packed;
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit priority;
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit expect;
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit break;
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit global;
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit property;
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit s_until_with;
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv::8 Unsuported token bit bufif0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit bufif0;
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit implements;
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv::8 Unsuported token bit tranif1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit tranif1;
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv::8 Unsuported token bit bufif1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit bufif1;
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv::8 Unsuported token bit highz1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit highz1;
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit before;
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit union;
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit static;
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit final;
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit until_with;
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit checker;
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endchecker;
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv::8 error in parsing: (syntax error, unexpected vLOCALPARAM, expecting vSYMBOL_ID or '#') bit localparam;
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit type;
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv::8 Unsuported token bit edge; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit edge;
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit s_until;
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit untyped;
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv::8 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or '#') bit integer;
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit eventually;
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv::8 error in parsing: (syntax error, unexpected vXOR, expecting vSYMBOL_ID or '#') bit xor;
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit local;
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit noshowcancelled;
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv::8 error in parsing: (syntax error, unexpected vIF, expecting vSYMBOL_ID or '#') bit if;
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv::8 Unsuported token bit medium; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit medium;
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv::8 error in parsing: (syntax error, unexpected netWAND, expecting vSYMBOL_ID or '#') bit wand;
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit illegal_bins;
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit always_latch;
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv::8 Unsuported token bit rnmos; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit rnmos;
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit export;
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit var;
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit liblist;
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv::8 error in parsing: (syntax error, unexpected netTRI, expecting vSYMBOL_ID or '#') bit tri;
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv::8 Unsuported token bit release; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit release;
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit logic;
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv::8 error in parsing: (syntax error, unexpected netTRI1, expecting vSYMBOL_ID or '#') bit tri1;
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv::8 Unsuported token bit notif1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit notif1;
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit randsequence;
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv::8 error in parsing: (syntax error, unexpected vEND, expecting vSYMBOL_ID or '#') bit end;
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv::8 Unsuported token bit join; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit join;
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv::8 error in parsing: (syntax error, unexpected vINOUT, expecting vSYMBOL_ID or '#') bit inout;
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv::8 Unsuported token bit scalared; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit scalared;
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit virtual;
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit int;
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit longint;
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit matches;
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv::8 error in parsing: (syntax error, unexpected vASSIGN, expecting vSYMBOL_ID or '#') bit assign;
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv::8 error in parsing: (syntax error, unexpected vENDSPECIFY, expecting vSYMBOL_ID or '#') bit endspecify;
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endproperty;
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit wildcard;
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit sync_reject_on;
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv::8 error in parsing: (syntax error, unexpected netTRI0, expecting vSYMBOL_ID or '#') bit tri0;
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit byte;
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv::8 Unsuported token bit endtable; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit endtable;
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv::8 error in parsing: (syntax error, unexpected vPOSEDGE, expecting vSYMBOL_ID or '#') bit posedge;
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv::8 Unsuported token bit supply0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit supply0;
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit interconnect;
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv::8 Unsuported token bit casez; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit casez;
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit let;
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv::8 Unsuported token bit pulldown; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit pulldown;
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit alias;
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv::8 Unsuported token bit supply1; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit supply1;
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv::8 Unsuported token bit highz0; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit highz0;
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit ifnone;
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv::8 error in parsing: (syntax error, unexpected vBEGIN, expecting vSYMBOL_ID or '#') bit begin;
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv::8 Unsuported token bit force; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit force;
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv::8 Unsuported token bit vectored; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit vectored;
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit context;
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit modport;
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv::8 error in parsing: (syntax error, unexpected vDEFAULT, expecting vSYMBOL_ID or '#') bit default;
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv::8 error in parsing: (syntax error, unexpected vENDTASK, expecting vSYMBOL_ID or '#') bit endtask;
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit within;
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit forkjoin;
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv::8 Unsuported token bit primitive; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit primitive;
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit randcase;
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit tagged;
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit continue;
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv::8 Unsuported token bit deassign; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit deassign;
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv::8 error in parsing: (syntax error, unexpected netTRIAND, expecting vSYMBOL_ID or '#') bit triand;
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit struct;
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit pulsestyle_onevent;
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit return;
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv::8 Unsuported token bit small; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') bit small;
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit iff;
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv::8 error in parsing: (syntax error, unexpected vELSE, expecting vSYMBOL_ID or '#') bit else;
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv::8 error in parsing: (syntax error, unexpected netTRIOR, expecting vSYMBOL_ID or '#') bit trior;
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endconfig;
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv::8 error in parsing: (syntax error, unexpected netREG, expecting vSYMBOL_ID or '#') bit reg;
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endinterface;
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') bit endprogram;
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8: error: invalid module item.
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv:8: error: invalid module item.
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8: error: invalid module item.
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8: error: invalid module item.
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8: error: invalid module item.
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8: error: invalid module item.
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8: error: invalid module item.
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8: error: invalid module item.
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8: error: invalid module item.
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8: error: invalid module item.
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8: error: invalid module item.
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8: error: invalid module item.
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8: error: invalid module item.
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8: error: invalid module item.
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8: error: invalid module item.
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8: error: invalid module item.
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8: error: invalid module item.
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8: error: invalid module item.
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8: error: invalid module item.
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8: error: invalid module item.
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8: error: invalid module item.
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8: error: invalid module item.
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8: error: invalid module item.
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8: error: invalid module item.
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8: error: invalid module item.
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8: error: invalid module item.
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8: error: invalid module item.
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8: error: invalid module item.
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8: error: invalid module item.
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8: error: invalid module item.
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8: error: invalid module item.
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8: error: invalid module item.
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8: error: invalid module item.
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8: error: invalid module item.
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8: error: invalid module item.
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv:8: error: invalid module item.
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8: error: invalid module item.
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8: error: invalid module item.
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8: error: invalid module item.
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8: error: invalid module item.
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv:8: error: invalid module item.
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8: error: invalid module item.
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8: error: invalid module item.
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8: error: invalid module item.
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8: error: invalid module item.
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8: error: invalid module item.
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8: error: invalid module item.
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv:8: error: invalid module item.
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8: error: invalid module item.
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8: error: invalid module item.
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8: error: invalid module item.
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8: error: invalid module item.
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8: error: invalid module item.
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8: error: invalid module item.
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8: error: invalid module item.
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8: error: invalid module item.
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8: error: invalid module item.
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8: error: invalid module item.
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8: error: invalid module item.
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8: error: invalid module item.
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8: error: invalid module item.
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8: error: invalid module item.
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8: error: invalid module item.
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8: error: invalid module item.
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8: error: invalid module item.
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8: error: invalid module item.
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv:8: error: invalid module item.
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8: error: invalid module item.
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv:8: error: invalid module item.
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8: error: invalid module item.
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8: error: invalid module item.
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv:8: error: invalid module item.
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8: error: invalid module item.
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8: error: invalid module item.
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8: error: invalid module item.
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8: error: invalid module item.
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8: error: invalid module item.
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8: error: invalid module item.
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8: error: invalid module item.
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8: error: invalid module item.
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8: error: invalid module item.
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv:8: error: invalid module item.
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8: error: invalid module item.
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8: error: invalid module item.
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8: error: invalid module item.
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8: error: invalid module item.
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv:8: error: invalid module item.
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv:8: error: invalid module item.
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8: error: invalid module item.
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8: error: invalid module item.
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8: error: invalid module item.
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8: error: invalid module item.
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8: error: invalid module item.
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8: error: invalid module item.
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8: error: invalid module item.
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8: error: invalid module item.
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8: error: invalid module item.
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8: error: invalid module item.
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8: error: invalid module item.
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8: error: invalid module item.
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8: error: invalid module item.
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8: error: invalid module item.
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv:8: error: invalid module item.
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv:8: error: invalid module item.
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8: error: invalid module item.
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8: error: invalid module item.
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8: error: invalid module item.
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8: error: invalid module item.
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8: error: invalid module item.
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv:8: error: invalid module item.
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8: error: invalid module item.
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8: error: invalid module item.
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8: error: invalid module item.
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8: error: invalid module item.
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8: error: invalid module item.
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8: error: invalid module item.
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8: error: invalid module item.
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8: error: invalid module item.
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8: error: invalid module item.
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8: error: invalid module item.
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8: error: invalid module item.
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8: error: invalid module item.
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8: error: invalid module item.
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8: error: invalid module item.
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8: error: invalid module item.
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8: error: invalid module item.
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8: error: invalid module item.
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8: error: invalid module item.
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8: error: invalid module item.
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8: error: invalid module item.
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8: error: invalid module item.
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8: error: invalid module item.
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8: error: invalid module item.
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8: error: invalid module item.
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8: error: invalid module item.
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8: error: invalid module item.
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8: error: invalid module item.
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8: error: invalid module item.
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8: error: invalid module item.
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8: error: invalid module item.
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8: error: invalid module item.
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8: error: invalid module item.
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8: error: invalid module item.
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8: error: invalid module item.
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8: error: invalid module item.
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8: error: invalid module item.
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8: error: invalid module item.
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8: error: invalid module item.
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv:8: error: invalid module item.
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8: error: invalid module item.
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv:8: error: invalid module item.
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8: error: invalid module item.
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8: error: invalid module item.
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8: error: invalid module item.
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8: error: invalid module item.
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8: error: invalid module item.
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv:8: error: invalid module item.
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8: error: invalid module item.
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8: error: invalid module item.
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8: error: invalid module item.
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8: error: invalid module item.
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8: error: invalid module item.
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8: error: invalid module item.
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8: error: invalid module item.
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8: error: invalid module item.
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8: error: invalid module item.
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv:8: error: invalid module item.
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8: error: invalid module item.
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8: error: invalid module item.
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8: error: invalid module item.
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8: error: invalid module item.
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8: error: invalid module item.
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8: error: invalid module item.
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8: error: invalid module item.
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8: error: invalid module item.
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8: error: invalid module item.
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv:8: error: invalid module item.
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8: error: invalid module item.
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8: error: invalid module item.
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8: error: invalid module item.
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8: error: invalid module item.
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8: error: invalid module item.
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8: error: invalid module item.
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv:8: error: invalid module item.
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8: error: invalid module item.
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8: error: invalid module item.
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8: error: invalid module item.
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8: error: invalid module item.
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8: error: invalid module item.
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8: error: invalid module item.
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv:8: error: invalid module item.
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8: error: invalid module item.
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv:8: error: invalid module item.
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv:8: error: invalid module item.
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8: error: invalid module item.
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8: error: invalid module item.
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8: error: invalid module item.
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8: error: invalid module item.
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv:8: error: invalid module item.
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8: error: invalid module item.
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8: error: invalid module item.
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv:8: error: invalid module item.
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv:8: error: invalid module item.
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8: error: invalid module item.
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8: error: invalid module item.
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8: error: invalid module item.
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8: error: invalid module item.
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8: error: invalid module item.
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8: error: invalid module item.
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv:8: error: invalid module item.
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv:8: error: invalid module item.
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8: error: invalid module item.
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8: error: invalid module item.
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv:8: error: invalid module item.
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8: error: invalid module item.
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8: error: invalid module item.
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8: error: invalid module item.
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8: error: invalid module item.
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8: error: invalid module item.
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv:8: error: invalid module item.
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8: error: invalid module item.
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8: error: invalid module item.
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8: error: invalid module item.
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8: error: invalid module item.
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8: error: invalid module item.
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8: error: invalid module item.
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8: error: invalid module item.
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8: error: invalid module item.
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8: error: invalid module item.
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8: error: invalid module item.
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8: error: invalid module item.
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8: error: invalid module item.
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8: error: invalid module item.
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8: error: invalid module item.
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8: error: invalid module item.
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8: error: invalid module item.
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv:8: error: invalid module item.
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8: error: invalid module item.
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8: error: invalid module item.
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8: error: invalid module item.
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8: error: invalid module item.
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8: error: invalid module item.
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8: error: invalid module item.
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv:8: error: invalid module item.
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8: error: invalid module item.
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv:8: error: invalid module item.
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8: error: invalid module item.
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8: error: invalid module item.
name: extendsdescription: The 'extends' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extends.sv:8:9: Parse error: unexpected token 'extends' (KW_extends).
name: uwiredescription: The 'uwire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_uwire.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType uwire]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: coverdescription: The 'cover' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cover.sv:8:9: Parse error: unexpected token 'cover' (KW_cover).
name: tranif0description: The 'tranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif0.sv:8:9: Parse error: unexpected token 'tranif0' (KW_tranif0).
name: casexdescription: The 'casex' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casex.sv:8:9: Parse error: unexpected token 'casex' (KW_casex).
name: coverpointdescription: The 'coverpoint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_coverpoint.sv:8:9: Parse error: unexpected token 'coverpoint' (KW_coverpoint).
name: untildescription: The 'until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until.sv:8:9: Parse error: unexpected token 'until' (KW_until).
name: endpackagedescription: The 'endpackage' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endpackage.sv:8:9: Parse error: unexpected token 'endpackage' (KW_endpackage).
name: programdescription: The 'program' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_program.sv:8:9: Parse error: unexpected token 'program' (KW_program).
name: dodescription: The 'do' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_do.sv:8:9: Parse error: unexpected token 'do' (KW_do).
name: endprimitivedescription: The 'endprimitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprimitive.sv:8:9: Parse error: unexpected token 'endprimitive' (KW_endprimitive).
name: sequencedescription: The 'sequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sequence.sv:8:9: Parse error: unexpected token 'sequence' (KW_sequence).
name: join_anydescription: The 'join_any' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_any.sv:8:9: Parse error: unexpected token 'join_any' (KW_join_any).
name: s_nexttimedescription: The 's_nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_nexttime.sv:8:9: Parse error: unexpected token 's_nexttime' (KW_s_nexttime).
name: nordescription: The 'nor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nor.sv:8:9: Parse error: unexpected token 'nor' (KW_nor).
name: genvardescription: The 'genvar' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_genvar.sv:8:9: Parse error: unexpected token 'genvar' (KW_genvar).
name: refdescription: The 'ref' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ref.sv:8:9: Parse error: unexpected token 'ref' (KW_ref).
name: incdirdescription: The 'incdir' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_incdir.sv:8:9: Parse error: unexpected token 'incdir' (KW_incdir).
name: nanddescription: The 'nand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nand.sv:8:9: Parse error: unexpected token 'nand' (KW_nand).
name: ordescription: The 'or' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_or.sv:8:9: Parse error: unexpected token 'or' (KW_or).
name: nmosdescription: The 'nmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nmos.sv:8:9: Parse error: unexpected token 'nmos' (KW_nmos).
name: wait_orderdescription: The 'wait_order' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait_order.sv:8:9: Parse error: unexpected token 'wait_order' (KW_wait_order).
name: weakdescription: The 'weak' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak.sv:8:9: Parse error: unexpected token 'weak' (KW_weak).
name: restrictdescription: The 'restrict' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_restrict.sv:8:9: Parse error: unexpected token 'restrict' (KW_restrict).
name: packagedescription: The 'package' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_package.sv:8:9: Parse error: unexpected token 'package' (KW_package).
name: crossdescription: The 'cross' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cross.sv:8:9: Parse error: unexpected token 'cross' (KW_cross).
name: pull0description: The 'pull0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull0.sv:8:9: Parse error: unexpected token 'pull0' (KW_pull0).
name: endsequencedescription: The 'endsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endsequence.sv:8:9: Parse error: unexpected token 'endsequence' (KW_endsequence).
name: solvedescription: The 'solve' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_solve.sv:8:9: Parse error: unexpected token 'solve' (KW_solve).
name: covergroupdescription: The 'covergroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_covergroup.sv:8:9: Parse error: unexpected token 'covergroup' (KW_covergroup).
name: voiddescription: The 'void' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_void.sv:8:9: Parse error: unexpected token 'void' (KW_void).
name: endclockingdescription: The 'endclocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclocking.sv:8:9: Parse error: unexpected token 'endclocking' (KW_endclocking).
name: endfunctiondescription: The 'endfunction' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endfunction.sv:8:9: Parse error: unexpected token 'endfunction' (KW_endfunction).
name: externdescription: The 'extern' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_extern.sv:8:9: Parse error: unexpected token 'extern' (KW_extern).
name: nettypedescription: The 'nettype' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nettype.sv:8:9: Parse error: unexpected token 'nettype' (KW_nettype).
name: signeddescription: The 'signed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_signed.sv']incdirs: []top_module: rc: 1zachjs-sv2v: incomplete declarationCallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:313:21 in main:Language.SystemVerilog.Parser.ParseDecl
name: stringdescription: The 'string' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_string.sv:8:9: Parse error: unexpected token 'string' (KW_string).
name: superdescription: The 'super' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_super.sv:8:9: Parse error: unexpected token 'super' (KW_super).
name: whiledescription: The 'while' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_while.sv:8:9: Parse error: unexpected token 'while' (KW_while).
name: negedgedescription: The 'negedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_negedge.sv:8:9: Parse error: unexpected token 'negedge' (KW_negedge).
name: bitdescription: The 'bit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bit.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType bit]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: functiondescription: The 'function' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_function.sv:8:9: Parse error: unexpected token 'function' (KW_function).
name: pulsestyle_ondetectdescription: The 'pulsestyle_ondetect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_ondetect.sv:8:9: Parse error: unexpected token 'pulsestyle_ondetect' (KW_pulsestyle_ondetect).
name: chandledescription: The 'chandle' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_chandle.sv:8:9: Parse error: unexpected token 'chandle' (KW_chandle).
name: insidedescription: The 'inside' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inside.sv:8:9: Parse error: unexpected token 'inside' (KW_inside).
name: configdescription: The 'config' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_config.sv:8:9: Parse error: unexpected token 'config' (KW_config).
name: librarydescription: The 'library' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_library.sv:8:9: Parse error: unexpected token 'library' (KW_library).
name: shortrealdescription: The 'shortreal' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortreal.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType shortreal]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: generatedescription: The 'generate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_generate.sv:8:9: Parse error: unexpected token 'generate' (KW_generate).
name: constdescription: The 'const' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_const.sv:8:9: Parse error: unexpected token 'const' (KW_const).
name: bufdescription: The 'buf' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_buf.sv:8:9: Parse error: unexpected token 'buf' (KW_buf).
name: usedescription: The 'use' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_use.sv:8:9: Parse error: unexpected token 'use' (KW_use).
name: instancedescription: The 'instance' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_instance.sv:8:9: Parse error: unexpected token 'instance' (KW_instance).
name: includedescription: The 'include' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_include.sv:8:9: Parse error: unexpected token 'include' (KW_include).
name: endgroupdescription: The 'endgroup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgroup.sv:8:9: Parse error: unexpected token 'endgroup' (KW_endgroup).
name: enumdescription: The 'enum' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_enum.sv:8:13: Parse error: unexpected token ';' (Sym_semi).
name: softdescription: The 'soft' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_soft.sv:8:9: Parse error: unexpected token 'soft' (KW_soft).
name: endcasedescription: The 'endcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endcase.sv:8:9: Parse error: unexpected token 'endcase' (KW_endcase).
name: accept_ondescription: The 'accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_accept_on.sv:8:9: Parse error: unexpected token 'accept_on' (KW_accept_on).
name: eventdescription: The 'event' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_event.sv:8:9: Parse error: unexpected token 'event' (KW_event).
name: sync_accept_ondescription: The 'sync_accept_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_accept_on.sv:8:9: Parse error: unexpected token 'sync_accept_on' (KW_sync_accept_on).
name: binsofdescription: The 'binsof' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_binsof.sv:8:9: Parse error: unexpected token 'binsof' (KW_binsof).
name: newdescription: The 'new' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_new.sv:8:9: Parse error: unexpected token 'new' (KW_new).
name: pmosdescription: The 'pmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pmos.sv:8:9: Parse error: unexpected token 'pmos' (KW_pmos).
name: pullupdescription: The 'pullup' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pullup.sv:8:9: Parse error: unexpected token 'pullup' (KW_pullup).
name: uniquedescription: The 'unique' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique.sv:8:9: Parse error: unexpected token 'unique' (KW_unique).
name: wiredescription: The 'wire' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wire.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType wire]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: always_combdescription: The 'always_comb' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_comb.sv:8:9: Parse error: unexpected token 'always_comb' (KW_always_comb).
name: triregdescription: The 'trireg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trireg.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType trireg]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: cmosdescription: The 'cmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cmos.sv:8:9: Parse error: unexpected token 'cmos' (KW_cmos).
name: endgeneratedescription: The 'endgenerate' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endgenerate.sv:8:9: Parse error: unexpected token 'endgenerate' (KW_endgenerate).
name: realdescription: The 'real' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_real.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType real]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: weak0description: The 'weak0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak0.sv:8:9: Parse error: unexpected token 'weak0' (KW_weak0).
name: always_ffdescription: The 'always_ff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_ff.sv:8:9: Parse error: unexpected token 'always_ff' (KW_always_ff).
name: strongdescription: The 'strong' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong.sv:8:9: Parse error: unexpected token 'strong' (KW_strong).
name: randdescription: The 'rand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rand.sv:8:9: Parse error: unexpected token 'rand' (KW_rand).
name: reject_ondescription: The 'reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reject_on.sv:8:9: Parse error: unexpected token 'reject_on' (KW_reject_on).
name: timeunitdescription: The 'timeunit' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeunit.sv:8:9: Parse error: unexpected token 'timeunit' (KW_timeunit).
name: s_eventuallydescription: The 's_eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_eventually.sv:8:9: Parse error: unexpected token 's_eventually' (KW_s_eventually).
name: impliesdescription: The 'implies' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implies.sv:8:9: Parse error: unexpected token 'implies' (KW_implies).
name: binddescription: The 'bind' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bind.sv:8:9: Parse error: unexpected token 'bind' (KW_bind).
name: shortintdescription: The 'shortint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_shortint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType shortint]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: constraintdescription: The 'constraint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_constraint.sv:8:9: Parse error: unexpected token 'constraint' (KW_constraint).
name: initialdescription: The 'initial' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_initial.sv:8:9: Parse error: unexpected token 'initial' (KW_initial).
name: unique0description: The 'unique0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unique0.sv:8:9: Parse error: unexpected token 'unique0' (KW_unique0).
name: waitdescription: The 'wait' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wait.sv:8:9: Parse error: unexpected token 'wait' (KW_wait).
name: automaticdescription: The 'automatic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_automatic.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTLifetime automatic]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: wordescription: The 'wor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wor.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType wor]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: puredescription: The 'pure' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pure.sv:8:9: Parse error: unexpected token 'pure' (KW_pure).
name: assumedescription: The 'assume' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assume.sv:8:9: Parse error: unexpected token 'assume' (KW_assume).
name: interfacedescription: The 'interface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interface.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: strong1description: The 'strong1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong1.sv:8:9: Parse error: unexpected token 'strong1' (KW_strong1).
name: macromoduledescription: The 'macromodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_macromodule.sv:8:9: Parse error: unexpected token 'macromodule' (KW_macromodule).
name: endmoduledescription: The 'endmodule' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endmodule.sv:8:9: Parse error: unexpected token 'endmodule' (KW_endmodule).
name: casedescription: The 'case' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_case.sv:8:9: Parse error: unexpected token 'case' (KW_case).
name: notif0description: The 'notif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif0.sv:8:9: Parse error: unexpected token 'notif0' (KW_notif0).
name: strong0description: The 'strong0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_strong0.sv:8:9: Parse error: unexpected token 'strong0' (KW_strong0).
name: rpmosdescription: The 'rpmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rpmos.sv:8:9: Parse error: unexpected token 'rpmos' (KW_rpmos).
name: moduledescription: The 'module' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_module.sv:8:9: Parse error: unexpected token 'module' (KW_module).
name: designdescription: The 'design' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_design.sv:8:9: Parse error: unexpected token 'design' (KW_design).
name: specifydescription: The 'specify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specify.sv:8:9: Parse error: unexpected token 'specify' (KW_specify).
name: repeatdescription: The 'repeat' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_repeat.sv:8:9: Parse error: unexpected token 'repeat' (KW_repeat).
name: realtimedescription: The 'realtime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_realtime.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType realtime]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: unsigneddescription: The 'unsigned' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_unsigned.sv']incdirs: []top_module: rc: 1zachjs-sv2v: incomplete declarationCallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:313:21 in main:Language.SystemVerilog.Parser.ParseDecl
name: taskdescription: The 'task' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_task.sv:8:9: Parse error: unexpected token 'task' (KW_task).
name: importdescription: The 'import' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_import.sv:8:9: Parse error: unexpected token 'import' (KW_import).
name: alwaysdescription: The 'always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always.sv:8:9: Parse error: unexpected token 'always' (KW_always).
name: pull1description: The 'pull1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pull1.sv:8:9: Parse error: unexpected token 'pull1' (KW_pull1).
name: thisdescription: The 'this' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_this.sv:8:9: Parse error: unexpected token 'this' (KW_this).
name: timedescription: The 'time' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_time.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType time]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: rtranif1description: The 'rtranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif1.sv:8:9: Parse error: unexpected token 'rtranif1' (KW_rtranif1).
name: first_matchdescription: The 'first_match' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_first_match.sv:8:9: Parse error: unexpected token 'first_match' (KW_first_match).
name: nexttimedescription: The 'nexttime' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_nexttime.sv:8:9: Parse error: unexpected token 'nexttime' (KW_nexttime).
name: rtrandescription: The 'rtran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtran.sv:8:9: Parse error: unexpected token 'rtran' (KW_rtran).
name: throughoutdescription: The 'throughout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_throughout.sv:8:9: Parse error: unexpected token 'throughout' (KW_throughout).
name: foreachdescription: The 'foreach' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_foreach.sv:8:9: Parse error: unexpected token 'foreach' (KW_foreach).
name: fordescription: The 'for' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_for.sv:8:9: Parse error: unexpected token 'for' (KW_for).
name: notdescription: The 'not' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_not.sv:8:9: Parse error: unexpected token 'not' (KW_not).
name: largedescription: The 'large' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_large.sv:8:9: Parse error: unexpected token 'large' (KW_large).
name: endclassdescription: The 'endclass' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endclass.sv:8:9: Parse error: unexpected token 'endclass' (KW_endclass).
name: s_alwaysdescription: The 's_always' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_always.sv:8:9: Parse error: unexpected token 's_always' (KW_s_always).
name: specparamdescription: The 'specparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_specparam.sv:8:9: Parse error: unexpected token 'specparam' (KW_specparam).
name: anddescription: The 'and' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_and.sv:8:9: Parse error: unexpected token 'and' (KW_and).
name: nulldescription: The 'null' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_null.sv:8:9: Parse error: unexpected token 'null' (KW_null).
name: foreverdescription: The 'forever' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forever.sv:8:9: Parse error: unexpected token 'forever' (KW_forever).
name: celldescription: The 'cell' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_cell.sv:8:9: Parse error: unexpected token 'cell' (KW_cell).
name: parameterdescription: The 'parameter' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_parameter.sv:8:9: Parse error: unexpected token 'parameter' (KW_parameter).
name: binsdescription: The 'bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bins.sv:8:9: Parse error: unexpected token 'bins' (KW_bins).
name: join_nonedescription: The 'join_none' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join_none.sv:8:9: Parse error: unexpected token 'join_none' (KW_join_none).
name: clockingdescription: The 'clocking' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_clocking.sv:8:9: Parse error: unexpected token 'clocking' (KW_clocking).
name: timeprecisiondescription: The 'timeprecision' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_timeprecision.sv:8:9: Parse error: unexpected token 'timeprecision' (KW_timeprecision).
name: withdescription: The 'with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_with.sv:8:9: Parse error: unexpected token 'with' (KW_with).
name: randcdescription: The 'randc' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randc.sv:8:9: Parse error: unexpected token 'randc' (KW_randc).
name: classdescription: The 'class' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_class.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: intersectdescription: The 'intersect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_intersect.sv:8:9: Parse error: unexpected token 'intersect' (KW_intersect).
name: defparamdescription: The 'defparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_defparam.sv:8:9: Parse error: unexpected token 'defparam' (KW_defparam).
name: distdescription: The 'dist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_dist.sv:8:9: Parse error: unexpected token 'dist' (KW_dist).
name: protecteddescription: The 'protected' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_protected.sv:8:9: Parse error: unexpected token 'protected' (KW_protected).
name: assertdescription: The 'assert' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assert.sv:8:9: Parse error: unexpected token 'assert' (KW_assert).
name: xnordescription: The 'xnor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xnor.sv:8:9: Parse error: unexpected token 'xnor' (KW_xnor).
name: disabledescription: The 'disable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_disable.sv:8:9: Parse error: unexpected token 'disable' (KW_disable).
name: trandescription: The 'tran' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tran.sv:8:9: Parse error: unexpected token 'tran' (KW_tran).
name: typedefdescription: The 'typedef' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_typedef.sv:8:9: Parse error: unexpected token 'typedef' (KW_typedef).
name: weak1description: The 'weak1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_weak1.sv:8:9: Parse error: unexpected token 'weak1' (KW_weak1).
name: showcancelleddescription: The 'showcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_showcancelled.sv:8:9: Parse error: unexpected token 'showcancelled' (KW_showcancelled).
name: ignore_binsdescription: The 'ignore_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ignore_bins.sv:8:9: Parse error: unexpected token 'ignore_bins' (KW_ignore_bins).
name: tabledescription: The 'table' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_table.sv:8:9: Parse error: unexpected token 'table' (KW_table).
name: rcmosdescription: The 'rcmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rcmos.sv:8:9: Parse error: unexpected token 'rcmos' (KW_rcmos).
name: outputdescription: The 'output' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_output.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTDir output]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: forkdescription: The 'fork' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_fork.sv:8:9: Parse error: unexpected token 'fork' (KW_fork).
name: inputdescription: The 'input' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_input.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTDir input]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: rtranif0description: The 'rtranif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rtranif0.sv:8:9: Parse error: unexpected token 'rtranif0' (KW_rtranif0).
name: packeddescription: The 'packed' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_packed.sv:8:9: Parse error: unexpected token 'packed' (KW_packed).
name: prioritydescription: The 'priority' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_priority.sv:8:9: Parse error: unexpected token 'priority' (KW_priority).
name: expectdescription: The 'expect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_expect.sv:8:9: Parse error: unexpected token 'expect' (KW_expect).
name: breakdescription: The 'break' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_break.sv:8:9: Parse error: unexpected token 'break' (KW_break).
name: globaldescription: The 'global' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_global.sv:8:9: Parse error: unexpected token 'global' (KW_global).
name: propertydescription: The 'property' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_property.sv:8:9: Parse error: unexpected token 'property' (KW_property).
name: s_until_withdescription: The 's_until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until_with.sv:8:9: Parse error: unexpected token 's_until_with' (KW_s_until_with).
name: bufif0description: The 'bufif0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif0.sv:8:9: Parse error: unexpected token 'bufif0' (KW_bufif0).
name: implementsdescription: The 'implements' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_implements.sv:8:9: Parse error: unexpected token 'implements' (KW_implements).
name: tranif1description: The 'tranif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tranif1.sv:8:9: Parse error: unexpected token 'tranif1' (KW_tranif1).
name: bufif1description: The 'bufif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_bufif1.sv:8:9: Parse error: unexpected token 'bufif1' (KW_bufif1).
name: highz1description: The 'highz1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz1.sv:8:9: Parse error: unexpected token 'highz1' (KW_highz1).
name: beforedescription: The 'before' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_before.sv:8:9: Parse error: unexpected token 'before' (KW_before).
name: uniondescription: The 'union' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_union.sv:8:14: Parse error: unexpected token ';' (Sym_semi).
name: staticdescription: The 'static' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_static.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTLifetime static]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: finaldescription: The 'final' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_final.sv:8:9: Parse error: unexpected token 'final' (KW_final).
name: until_withdescription: The 'until_with' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_until_with.sv:8:9: Parse error: unexpected token 'until_with' (KW_until_with).
name: checkerdescription: The 'checker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_checker.sv:8:9: Parse error: unexpected token 'checker' (KW_checker).
name: endcheckerdescription: The 'endchecker' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endchecker.sv:8:9: Parse error: unexpected token 'endchecker' (KW_endchecker).
name: localparamdescription: The 'localparam' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_localparam.sv:8:9: Parse error: unexpected token 'localparam' (KW_localparam).
name: typedescription: The 'type' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_type.sv:8:9: Parse error: unexpected token 'type' (KW_type).
name: edgedescription: The 'edge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_edge.sv:8:9: Parse error: unexpected token 'edge' (KW_edge).
name: s_untildescription: The 's_until' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_s_until.sv:8:9: Parse error: unexpected token 's_until' (KW_s_until).
name: untypeddescription: The 'untyped' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_untyped.sv:8:9: Parse error: unexpected token 'untyped' (KW_untyped).
name: integerdescription: The 'integer' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_integer.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType integer]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: eventuallydescription: The 'eventually' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_eventually.sv:8:9: Parse error: unexpected token 'eventually' (KW_eventually).
name: xordescription: The 'xor' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_xor.sv:8:9: Parse error: unexpected token 'xor' (KW_xor).
name: localdescription: The 'local' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_local.sv:8:9: Parse error: unexpected token 'local' (KW_local).
name: noshowcancelleddescription: The 'noshowcancelled' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_noshowcancelled.sv:8:9: Parse error: unexpected token 'noshowcancelled' (KW_noshowcancelled).
name: ifdescription: The 'if' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_if.sv:8:9: Parse error: unexpected token 'if' (KW_if).
name: mediumdescription: The 'medium' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_medium.sv:8:9: Parse error: unexpected token 'medium' (KW_medium).
name: wanddescription: The 'wand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wand.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType wand]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: illegal_binsdescription: The 'illegal_bins' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_illegal_bins.sv:8:9: Parse error: unexpected token 'illegal_bins' (KW_illegal_bins).
name: always_latchdescription: The 'always_latch' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_always_latch.sv:8:9: Parse error: unexpected token 'always_latch' (KW_always_latch).
name: rnmosdescription: The 'rnmos' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_rnmos.sv:8:9: Parse error: unexpected token 'rnmos' (KW_rnmos).
name: exportdescription: The 'export' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_export.sv:8:9: Parse error: unexpected token 'export' (KW_export).
name: vardescription: The 'var' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_var.sv:8:9: Parse error: unexpected token 'var' (KW_var).
name: liblistdescription: The 'liblist' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_liblist.sv:8:9: Parse error: unexpected token 'liblist' (KW_liblist).
name: tridescription: The 'tri' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType tri]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: releasedescription: The 'release' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_release.sv:8:9: Parse error: unexpected token 'release' (KW_release).
name: logicdescription: The 'logic' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_logic.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType logic]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: tri1description: The 'tri1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri1.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType tri1]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: notif1description: The 'notif1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_notif1.sv:8:9: Parse error: unexpected token 'notif1' (KW_notif1).
name: randsequencedescription: The 'randsequence' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randsequence.sv:8:9: Parse error: unexpected token 'randsequence' (KW_randsequence).
name: enddescription: The 'end' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_end.sv:8:9: Parse error: unexpected token 'end' (KW_end).
name: joindescription: The 'join' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_join.sv:8:9: Parse error: unexpected token 'join' (KW_join).
name: inoutdescription: The 'inout' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_inout.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTDir inout]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: scalareddescription: The 'scalared' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_scalared.sv:8:9: Parse error: unexpected token 'scalared' (KW_scalared).
name: virtualdescription: The 'virtual' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_virtual.sv:8:9: Parse error: unexpected token 'virtual' (KW_virtual).
name: intdescription: The 'int' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_int.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType int]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: longintdescription: The 'longint' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_longint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType longint]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: matchesdescription: The 'matches' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_matches.sv:8:9: Parse error: unexpected token 'matches' (KW_matches).
name: assigndescription: The 'assign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_assign.sv:8:9: Parse error: unexpected token 'assign' (KW_assign).
name: endspecifydescription: The 'endspecify' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endspecify.sv:8:9: Parse error: unexpected token 'endspecify' (KW_endspecify).
name: endpropertydescription: The 'endproperty' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endproperty.sv:8:9: Parse error: unexpected token 'endproperty' (KW_endproperty).
name: wildcarddescription: The 'wildcard' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_wildcard.sv:8:9: Parse error: unexpected token 'wildcard' (KW_wildcard).
name: sync_reject_ondescription: The 'sync_reject_on' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_sync_reject_on.sv:8:9: Parse error: unexpected token 'sync_reject_on' (KW_sync_reject_on).
name: tri0description: The 'tri0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tri0.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType tri0]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: bytedescription: The 'byte' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_byte.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType byte]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: endtabledescription: The 'endtable' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtable.sv:8:9: Parse error: unexpected token 'endtable' (KW_endtable).
name: posedgedescription: The 'posedge' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_posedge.sv:8:9: Parse error: unexpected token 'posedge' (KW_posedge).
name: supply0description: The 'supply0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply0.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType supply0]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: interconnectdescription: The 'interconnect' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_interconnect.sv:8:9: Parse error: unexpected token 'interconnect' (KW_interconnect).
name: casezdescription: The 'casez' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_casez.sv:8:9: Parse error: unexpected token 'casez' (KW_casez).
name: letdescription: The 'let' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_let.sv:8:9: Parse error: unexpected token 'let' (KW_let).
name: pulldowndescription: The 'pulldown' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulldown.sv:8:9: Parse error: unexpected token 'pulldown' (KW_pulldown).
name: aliasdescription: The 'alias' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_alias.sv:8:9: Parse error: unexpected token 'alias' (KW_alias).
name: supply1description: The 'supply1' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_supply1.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType supply1]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: highz0description: The 'highz0' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_highz0.sv:8:9: Parse error: unexpected token 'highz0' (KW_highz0).
name: ifnonedescription: The 'ifnone' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_ifnone.sv:8:9: Parse error: unexpected token 'ifnone' (KW_ifnone).
name: begindescription: The 'begin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_begin.sv:8:9: Parse error: unexpected token 'begin' (KW_begin).
name: forcedescription: The 'force' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_force.sv:8:9: Parse error: unexpected token 'force' (KW_force).
name: vectoreddescription: The 'vectored' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_vectored.sv:8:9: Parse error: unexpected token 'vectored' (KW_vectored).
name: contextdescription: The 'context' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_context.sv:8:9: Parse error: unexpected token 'context' (KW_context).
name: modportdescription: The 'modport' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_modport.sv:8:9: Parse error: unexpected token 'modport' (KW_modport).
name: defaultdescription: The 'default' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_default.sv:8:9: Parse error: unexpected token 'default' (KW_default).
name: endtaskdescription: The 'endtask' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endtask.sv:8:9: Parse error: unexpected token 'endtask' (KW_endtask).
name: withindescription: The 'within' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_within.sv:8:9: Parse error: unexpected token 'within' (KW_within).
name: forkjoindescription: The 'forkjoin' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_forkjoin.sv:8:9: Parse error: unexpected token 'forkjoin' (KW_forkjoin).
name: primitivedescription: The 'primitive' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_primitive.sv:8:9: Parse error: unexpected token 'primitive' (KW_primitive).
name: randcasedescription: The 'randcase' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_randcase.sv:8:9: Parse error: unexpected token 'randcase' (KW_randcase).
name: taggeddescription: The 'tagged' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_tagged.sv:8:9: Parse error: unexpected token 'tagged' (KW_tagged).
name: continuedescription: The 'continue' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_continue.sv:8:9: Parse error: unexpected token 'continue' (KW_continue).
name: deassigndescription: The 'deassign' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_deassign.sv:8:9: Parse error: unexpected token 'deassign' (KW_deassign).
name: trianddescription: The 'triand' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_triand.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType triand]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: structdescription: The 'struct' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_struct.sv:8:15: Parse error: unexpected token ';' (Sym_semi).
name: pulsestyle_oneventdescription: The 'pulsestyle_onevent' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_pulsestyle_onevent.sv:8:9: Parse error: unexpected token 'pulsestyle_onevent' (KW_pulsestyle_onevent).
name: returndescription: The 'return' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_return.sv:8:9: Parse error: unexpected token 'return' (KW_return).
name: smalldescription: The 'small' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_small.sv:8:9: Parse error: unexpected token 'small' (KW_small).
name: iffdescription: The 'iff' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_iff.sv:8:9: Parse error: unexpected token 'iff' (KW_iff).
name: elsedescription: The 'else' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_else.sv:8:9: Parse error: unexpected token 'else' (KW_else).
name: triordescription: The 'trior' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_trior.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType trior]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: endconfigdescription: The 'endconfig' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endconfig.sv:8:9: Parse error: unexpected token 'endconfig' (KW_endconfig).
name: regdescription: The 'reg' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_reg.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType reg]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: endinterfacedescription: The 'endinterface' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endinterface.sv:8:9: Parse error: unexpected token 'endinterface' (KW_endinterface).
name: endprogramdescription: The 'endprogram' keyword should be reservedshould_fail: 1tags: 5.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/keywords/5.6.2--keyword_endprogram.sv:8:9: Parse error: unexpected token 'endprogram' (KW_endprogram).
name: system-functionsdescription: Calling system functionsshould_fail: 0tags: 5.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.3--system-functions.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.3--system-functions.sv' to AST representation.Generating RTLIL representation for module `\systemfn'.hello worldSuccessfully finished Verilog frontend.
name: system-functionsdescription: Calling system functionsshould_fail: 0tags: 5.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.3--system-functions.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.3--system-functions.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.3--system-functions.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: include-directivedescription: Include empty fileshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv:8:10: error: could not find or open include file`include "/dev/null" ^
name: pragma-directivedescription: Try to set a pragmashould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv:9:9: error: expected member`pragma protect ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv:11:9: error: expected member`pragma protect end ^~~~~~~
name: preproc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv:7:10: error: could not find or open include file`include "foo.svh" ^
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv:7:25: error: numeric literals must not start with a leading underscoreparameter int foo = 32'H_7f_FF_; ^
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:27: error: unknown macro or compiler directive '`DIGITS'parameter int foo = 32 'o `DIGITS; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:34: error: expected vector literal digitsparameter int foo = 32 'o `DIGITS; ^
name: pragma-directivedescription: Try to set a pragmashould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv']incdirs: []top_module: rc: 0
name: desc_test_3description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_3.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_3.sv
name: desc_test_6description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_6.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_6.sv
name: desc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_2.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_2.sv
name: desc_test_13description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv']incdirs: []top_module: rc: 10%Error: Internal Error: ../V3LinkLevel.cpp:93: No module found to process%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv
name: desc_test_7description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_7.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_7.sv
name: desc_test_17description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_17.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_17.sv
name: desc_test_4description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_4.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_4.sv
name: desc_test_16description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_16.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_16.sv
name: desc_test_10description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_10.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_10.sv
name: desc_test_8description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_8.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_8.sv
name: desc_test_12description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_12.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_12.sv
name: desc_test_11description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_11.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_11.sv
name: desc_test_1description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_1.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_1.sv
name: desc_test_9description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_9.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_9.sv
name: desc_test_0description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_0.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_0.sv
name: desc_test_5description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_5.sv']incdirs: []top_module: rc: 10%Error: No top level module found%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_5.sv
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bz' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bxxxx' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h1' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'shf' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bzzzz' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv
name: resetall-directivedescription: Check for the resetall directiveshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv:8: Unimplemented compiler directive or undefined macro `resetall.
name: resetall-directivedescription: Check for the resetall directiveshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv::11 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unconnected-drivedescription: Unconnected drive keywordsshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-unconnected-drive.sv::12 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: celldefinedescription: Celldefine checkshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-celldefine.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-celldefine.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-celldefine.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-celldefine.sv::10 error in parsing: (syntax error, unexpected vENDMODULE)endmodule
name: debug-linedescription: Debugging compiler directivesshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug-line.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug-line.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug-line.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug-line.sv::10 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: debug-directivesdescription: Debugging compiler directivesshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-debug.sv::9 __FILE__ define cannot be found initial $display("At %s @ %d\n", `__FILE__, `__LINE__);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: timescale-directivedescription: Set timescaleshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-timescale.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-timescale.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-timescale.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-timescale.sv::11 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: define-directivedescription: Define and undef checksshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-define.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-define.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-define.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }ERROR (3)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-define.sv::22 undefineall define cannot be found`undefineallAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/verilog_flex.l]load_define::736
name: default-nettypedescription: Default nettype checkshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-default-nettype.sv::11 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: include-directivedescription: Include empty fileshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }WARNING (3)::ARG_ERROR /dev/null::1 File (/dev/null) has an unsupported extension (), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-include.sv::11 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: pragma-directivedescription: Try to set a pragmashould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-pragma.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: begin-keywordsdescription: Begin keywords checkshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-begin-keywords.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-begin-keywords.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-begin-keywords.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: desc_test_3description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_6description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_13description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_13.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)package foo_pkg;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_7description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_17description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_4description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_16description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_10description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_8description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_12description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_11description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_1description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_9description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_0description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_5description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_15description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_15.sv::12 error in parsing: (syntax error, unexpected vENDMODULE)endmoduleERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_18description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: desc_test_14description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/desc/desc_test_14.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)package foo_pkg;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_8description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_10description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_11description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_7description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_3description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_4description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_0description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_1description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }ERROR (3)::ARG_ERROR cannot open file: foo.svhAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_util.cpp]open_file::121
name: preproc_test_6description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_5description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_13description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_12description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: preproc_test_9description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR error in parsing: (syntax error, unexpected $end, expecting vMODULE or preDEFAULT_NETTYPE)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_16description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'Sb0000;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_37description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_30description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_68description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'D1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hFEEDFACE;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H7fFF;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bxxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar, baz);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7_7_7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'so7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H_7f_FF_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hdeadbeef;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_49description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'So7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'B0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'sb1111;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'O7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b x;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bzzzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx__;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'ozz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: resetall-directivedescription: Check for the resetall directiveshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.6.4--compiler-directives-resetall.sv']incdirs: []top_module: rc: 0
name: preproc_test_8description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_8.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_10description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_10.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_11description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_11.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_7description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_7.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_3description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_3.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_3.sv:7: warning: macro EXPAND_TO_STRING undefined (and assumed null) at this point.No top level modules, and no -s option.Segmentation fault (core dumped)
name: preproc_test_4description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_4.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_0description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_0.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_1description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_1.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv:8: Include file foo.svh not foundNo top level modules, and no -s option.
name: preproc_test_6description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_6.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_5description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_5.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: preproc_test_2description: Testshould_fail: 0tags: 5.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv:7:19: Lexical error: Could not find file "foo.svh", included from "/home/travis/build/SymbiFlow/sv-tests/tests/generic/preproc/preproc_test_2.sv"
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv:7:25: error: numeric literals must not start with a leading underscoreparameter int foo = 32'H_7f_FF_; ^
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:27: error: unknown macro or compiler directive '`DIGITS'parameter int foo = 32 'o `DIGITS; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:34: error: expected vector literal digitsparameter int foo = 32 'o `DIGITS; ^
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bz' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bxxxx' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h1' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'shf' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bzzzz' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv
name: integers-left-padding-bitdescription: Automatic left padding of literal numbers using single-bit valueshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv:11: syntax error, unexpected $undefined
name: integers-underscoresdescription: Automatic left padding of literal numbers using single-bit valueshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integers-left-paddingdescription: Automatic left padding of literal constant numbersshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv:14)Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv:15)Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv:18)Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integers-unsized-illegaldescription: Integer literal constantsshould_fail: 1tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized-illegal.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized-illegal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized-illegal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized-illegal.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [31:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized-illegal.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = 4af; // is illegal (hexadecimal format requires 'h)ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: integers-sizeddescription: Integer literal constantsshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-sized.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-sized.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-sized.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-sized.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [3:0] a;
name: integers-tokendescription: Testing the integer variable typeshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-token.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-token.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-token.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: integers-sized-illegaldescription: Integer literal constantsshould_fail: 1tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed-illegal.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed-illegal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed-illegal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed-illegal.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [7:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed-illegal.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = 8'd-6;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: integers-left-padding-bitdescription: Automatic left padding of literal numbers using single-bit valueshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding-bit.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [15:0] a, b, c, d;
name: integers-underscoresdescription: Automatic left padding of literal numbers using single-bit valueshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [31:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-underscores.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') c = 32 'h 12ab_f001; // 32-bit hexadecimal numberERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: integers-left-paddingdescription: Automatic left padding of literal constant numbersshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [11:0] a, b, c, d;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-left-padding.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = 'h x; // yields xxxERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: integers-unsizeddescription: Integer literal constantsashould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [31:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-unsized.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') a = 'h 837FF; // is a hexadecimal numberERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: integers-signeddescription: Integer literal constantsshould_fail: 0tags: 5.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [7:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.1--integers-signed.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = -8'd 6; // this defines the two's-complement of 6,ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_16description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'Sb0000;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_37description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_30description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_68description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'D1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hFEEDFACE;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H7fFF;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bxxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar, baz);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7_7_7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'so7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H_7f_FF_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hdeadbeef;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_49description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'So7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'B0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'sb1111;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'O7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b x;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bzzzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx__;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'ozz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv:7:25: error: numeric literals must not start with a leading underscoreparameter int foo = 32'H_7f_FF_; ^
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:27: error: unknown macro or compiler directive '`DIGITS'parameter int foo = 32 'o `DIGITS; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7:34: error: expected vector literal digitsparameter int foo = 32 'o `DIGITS; ^
name: real-constantsdescription: Examples of real literal constantsshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv']incdirs: []top_module: rc: 0%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:11: Implicit conversion of real to integer%Warning-REALCVT: Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:12: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:13: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:14: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:15: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:16: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:17: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:18: Implicit conversion of real to integer%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:19: Implicit conversion of real to integer
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bz' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bxxxx' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h1' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'shf' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `WIDTH%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'bx' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv:7: Define or directive not defined: `DIGITS%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '1'h0' generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv:7: Operator VAR 'foo' expects 32 bits on the Initial value, but Initial value's CONST '4'bzzzz' generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: Define or directive not defined: `DIGITS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: syntax error, unexpected '(', expecting ';'%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv
name: real-constantsdescription: Examples of real literal constantsshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv' to AST representation.Generating RTLIL representation for module `\top'.Warning: converting real value 1.200000e+00 to binary 1 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:11.Warning: converting real value 1.000000e-01 to binary 0 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:12.Warning: converting real value 2.394263e+03 to binary 2394 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:13.Warning: converting real value 1.200000e+12 to binary 1704124416 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:14.Warning: converting real value 1.300000e-02 to binary 0 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:15.Warning: converting real value 1.000000e-01 to binary 0 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:16.Warning: converting real value 2.300000e+11 to binary 32'10001101000100010111110000000000 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:17.Warning: converting real value 2.900000e-01 to binary 0 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:18.Warning: converting real value 2.361238e-10 to binary 0 at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv:19.Successfully finished Verilog frontend.
name: real-constants-illegaldescription: Examples of real literal constantsshould_fail: 1tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv:11: syntax error, unexpected '.'
name: real-tokendescription: Testing the real variable typeshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv:8: syntax error, unexpected TOK_REAL
name: real-constantsdescription: Examples of real literal constantsshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [31:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv::11 error in parsing: (syntax error, unexpected '.', expecting ';') a = 1.2;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: real-constants-illegaldescription: Examples of real literal constantsshould_fail: 1tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [31:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv::11 error in parsing: (syntax error, unexpected '.') a = .12;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: real-tokendescription: Testing the real variable typeshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') real a;
name: number_test_16description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_16.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'Sb0000;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_37description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_37.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_30description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_30.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_68description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_68.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'Sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_12description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_12.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_23description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_23.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_2description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_2.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_72description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_72.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_66description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_66.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_47description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_47.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o 7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_69description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_69.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_1description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_1.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_3description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_3.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = '1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_38description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_38.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_25description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_25.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_76description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_76.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_56description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_56.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_36description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_36.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_27description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_27.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'D1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_57description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_57.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_73description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_73.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_21description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_21.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_4description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_4.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_65description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_65.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hFEEDFACE;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_50description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_50.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_62description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_62.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H7fFF;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_13description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_13.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bxxxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_9description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_9.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_0description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_0.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter foo = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_20description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_20.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar, baz);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_10description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_10.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'bx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_45description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_45.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7_7_7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_19description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_19.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_48description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_48.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'so7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_31description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_31.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_34description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_34.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_63description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_63.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'H_7f_FF_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'o `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hdeadbeef;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_49description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'So7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'B0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16 'b `DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'sb1111;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sd1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'h `DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'sh7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'd`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = `WIDTH'h`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oXX;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'O7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'o0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1'b0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o7;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'o`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b x;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx_;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 16'b`DIGITS;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'h0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 1 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'h`DIGITS();ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 4'bzzzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32 'd 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'oZZ;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'dx__;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'b 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'ozz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'hzz;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 'd0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv::7 error in parsing: (syntax error, unexpected vPARAMETER, expecting vMODULE or preDEFAULT_NETTYPE)parameter int foo = 32'd`DIGITS(bar);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: real-constantsdescription: Examples of real literal constantsshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv']incdirs: []top_module: rc: 0
name: number_test_55description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_55.sv:7: syntax errorI give up.
name: number_test_60description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_60.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_64description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_64.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_49description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_49.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_26description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_26.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_7description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_7.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_22description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_22.sv:7: syntax errorI give up.
name: number_test_70description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_70.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_58description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: warning: macro WIDTH undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_58.sv:7: syntax errorI give up.
name: number_test_15description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_15.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_29description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_29.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_74description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_74.sv:7: syntax errorI give up.
name: number_test_67description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_67.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_43description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_43.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_41description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: warning: macro WIDTH undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_41.sv:7: syntax errorI give up.
name: number_test_61description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_61.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_77description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: warning: macro WIDTH undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_77.sv:7: syntax errorI give up.
name: number_test_51description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_51.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_39description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_39.sv:7: syntax errorI give up.
name: number_test_46description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_46.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_42description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_42.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_6description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_6.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_44description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_44.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_54description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_54.sv:7: syntax errorI give up.
name: number_test_18description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_18.sv:7: syntax errorI give up.
name: number_test_11description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_11.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_32description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_32.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_17description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_17.sv:7: syntax errorI give up.
name: number_test_59description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_59.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_8description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_8.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_35description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_35.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_75description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_75.sv:7: syntax errorI give up.
name: number_test_14description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_14.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_28description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_28.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_53description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_53.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_33description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_33.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_5description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_5.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_52description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_52.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_71description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_71.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_24description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_24.sv:7: sorry: parameter declarations in the $root scope are not yet supported.
name: number_test_40description: Testshould_fail: 0tags: 5.6.4 5.7.1 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: warning: macro DIGITS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/number/number_test_40.sv:7: syntax errorI give up.
name: real-constantsdescription: Examples of real literal constantsshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants.sv']incdirs: []top_module: rc: 0module top; reg [31:0] a; initial begin ; a = 1.2; a = 0.1; a = 2394.26331; a = 1.2E12; a = 1.30e-2; a = 0.1e-0; a = 23E10; a = 29E-2; a = 236.123_763_e-12; endendmodule
name: real-constants-illegaldescription: Examples of real literal constantsshould_fail: 1tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-constants-illegal.sv:11:9: Parse error: unexpected token '.' (Sym_dot).
name: real-tokendescription: Testing the real variable typeshould_fail: 0tags: 5.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.7.2-real-token.sv']incdirs: []top_module: rc: 0module top; real a;endmodule
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:14:9: error: language feature not yet supported a = 1fs; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:15:9: error: language feature not yet supported a = 1ps; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:16:9: error: language feature not yet supported a = 1ns; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:17:9: error: language feature not yet supported a = 1us; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:18:9: error: language feature not yet supported a = 1ms; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:19:9: error: language feature not yet supported a = 1s; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:22:9: error: language feature not yet supported a = 2.1ms; ^~~~~
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 0
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:14: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:15: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:16: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:17: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:18: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:19: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:22: syntax error, unexpected TIME NUMBER, expecting TYPE-IDENTIFIER%Error: Exiting due to 7 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:11: syntax error, unexpected ';', expecting '(' or '['
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv::11 Unsuported token time a; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv::11 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') time a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = 1fs;
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:24: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:24: error: invalid module item.
name: time-literalsdescription: Examples of time literalsshould_fail: 0tags: 5.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.8-time-literals.sv:14:9: Parse error: unexpected token '1fs' (Lit_time).
name: string-word-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv:8:22: error: value of type 'bit[23:0]' cannot be assigned to type 'unpacked array [24:0] of 'bit'' bit a[8 * 3 : 0] = "hi0"; ^ ~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv:9:22: error: value of type 'bit[23:0]' cannot be assigned to type 'unpacked array [3:0] of 'byte'' byte b[3 : 0] = "hi2"; ^ ~~~~~
name: string-broken-linedescription: Basic broken line string exampleshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv' to AST representation.broken \Generating RTLIL representation for module `\top'. lineSuccessfully finished Verilog frontend.
name: string-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-assignment.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') byte a;
name: string-word-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') bit a[8 * 3 : 0] = "hi0";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(') byte b[3 : 0] = "hi2";
name: string-basicdescription: Basic string exampleshould_fail: 0tags: 5.9 5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-basics.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: string-broken-linedescription: Basic broken line string exampleshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: string-word-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv:8: error: Cannot assign to array a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv:9: error: Cannot assign to array b. Did you forget a word index?Elaboration failed
name: string-broken-linedescription: Basic broken line string exampleshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv:10: Missing close quote of string./home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-broken-line.sv:11: Missing close quote of string.I give up.
name: string-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-assignment.sv']incdirs: []top_module: rc: 0module top; reg [7:0] a; reg [7:0] b; reg [7:0] c; initial begin ; a = "a"; b = "b"; c = "c"; endendmodule
name: string-word-assignmentdescription: String assignment testsshould_fail: 0tags: 5.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9-string-word-assignment.sv']incdirs: []top_module: rc: 1zachjs-sv2v: non-vector type byte cannot have a packed dimesions:[(3,0)]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/AST/Type.hs:104:5 in main:Language.SystemVerilog.AST.Type
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: 0
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: 0
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: 0
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv' to AST representation.Generating RTLIL representation for module `\top'.newline tab backslash \quote "vertical tab vform feed fbell aoctal Shex x12Successfully finished Verilog frontend.
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv::13 error in parsing: (syntax error, unexpected vNUMBER, expecting ')') $display("quote \"");ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: string-special-charsdescription: Special characters in stringsshould_fail: 0tags: 5.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.9.1-string-special-chars.sv']incdirs: []top_module: rc: 0
name: structure-replicationdescription: Structure replication assignment testsshould_fail: 0tags: 5.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-replication.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-replication.sv:9: Unsupported: Unpacked array in packed struct/union%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-replication.sv
name: structure-arraysdescription: Structure array assignment testsshould_fail: 0tags: 5.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays.sv']incdirs: []top_module: rc: 0%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays.sv:8: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
name: structuredescription: Structure assignment testsshould_fail: 0tags: 5.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structures.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structures.sv:18: syntax error, unexpected int, expecting FLOATING-POINT NUMBER or IDENTIFIER or INTEGER NUMBER or default%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structures.sv:20: syntax error, unexpected ':', expecting "'{"%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structures.sv
name: structure-arrays-illegaldescription: Structure array assignment testsshould_fail: 1tags: 5.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays-illegal.sv']incdirs: []top_module: rc: 10%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays-illegal.sv:8: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays-illegal.sv:14: Assignment pattern with too many elements%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.10-structure-arrays-illegal.sv
name: arrays-key-indexdescription: Basic arrays testshould_fail: 0tags: 5.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-key-index.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-key-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-key-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-key-index.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int triple [1:3];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-key-index.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') triple b = '{1:1, default:0};
name: arrays-replicationdescription: Basic arrays testshould_fail: 0tags: 5.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-replication.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-replication.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-replication.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays-replication.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') int n[1:2][1:6] = '{2{'{3{4, 5}}}};
name: arraysdescription: Basic arrays testshould_fail: 0tags: 5.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.11-arrays.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') int n[1:2][1:3] = '{'{0,1,2},'{3{4}}};
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 0
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: 0
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: 0
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 0
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 0
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: 0
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: 0
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 0
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 0
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: 10%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv:13: Unsupported: Multiple top level modules: topb and topa%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv:13: Fix, or use --top-module option to select which you want.%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv:17: Unsupported: Multiple top level modules: topc and topb%Error-MULTITOP: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv:17: Fix, or use --top-module option to select which you want.%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: 0
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 0
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv' to AST representation.Generating RTLIL representation for module `\topa'.Generating RTLIL representation for module `\topb'.Generating RTLIL representation for module `\topc'.Successfully finished Verilog frontend.
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(') bit b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv::15 error in parsing: (syntax error, unexpected '(') (* full_case, parallel_case *)ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [7:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv::14 error in parsing: (syntax error, unexpected '*') a = b + (* mode = "cla" *) c;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv::8 error in parsing: (syntax error, unexpected '(', expecting vMODULE or preDEFAULT_NETTYPE)(* optimize_power *)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv::9 error in parsing: (syntax error, unexpected '(') (* fsm_state *) logic [7:0] a;
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv::9 error in parsing: (syntax error, unexpected ',', expecting '(') bit a, b, c, d;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv::12 error in parsing: (syntax error, unexpected '*') a = b ? (* no_glitch *) c : d;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 0
name: attributes-moduledescription: Assing attributes to a moduleshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-module.sv']incdirs: []top_module: rc: 0
name: attributes-variabledescription: Assing attributes to a variableshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-variable.sv']incdirs: []top_module: rc: 0
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 0
name: attributes-casedescription: Assing attributes to a case statementshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-case.sv']incdirs: []top_module: rc: 0module top; wire [1:0] a; reg b; initial begin ; (* full_case, parallel_case *) case (a) 2'b00: b = 0; 2'b01, 2'b10: b = 1; default: b = 0; endcase (* full_case = 1 *) (* parallel_case = 1 *) case (a) 2'b00: b = 0; 2'b01, 2'b10: b = 1; default: b = 0; endcase (* full_case, parallel_case = 0 *) case (a) 2'b00: b = 0; 2'b01, 2'b10: b = 1; default: b = 0; endcase endendmodule
name: attributes-operatordescription: Assing attributes to an operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-operator.sv:14:13: Parse error: unexpected token '(*' (Sym_paren_l_aster).
name: attributes-conditionaldescription: Assing attributes to a conditional operatorshould_fail: 0tags: 5.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.12-attributes-conditional.sv:12:13: Parse error: unexpected token '(*' (Sym_paren_l_aster).
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv:11:37: error: invalid member access for type 'string' $display("length check: %d\n", a.len()); ~^~~~
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv:11:40: error: unknown built-in method 'size' $display ("Array size %d\n", array.size()); ^~~~
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 0
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 0
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv:11: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv:11: Unknown built-in array method 'VARREF 'array''%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv:8: syntax error, unexpected '=', expecting '(' or '['
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\array.size' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv:11.
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv::11 error in parsing: (syntax error, unexpected ')') $display("length check: %d\n", a.len());ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv::8 error in parsing: (syntax error, unexpected ']') reg [7:0] array [3];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv::11 error in parsing: (syntax error, unexpected ')') $display ("Array size %d\n", array.size());ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 0
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv:11: error: No function named `array.size' found in this context (top).1 error(s) during elaboration.
name: builtin-methods-stringdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-strings.sv:8:3: Parse error: unexpected token 'string' (KW_string).
name: builtin-methods-arraysdescription: Check if built-in methods can be calledshould_fail: 0tags: 5.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-5/5.13-builtin-methods-arrays.sv:11:44: Parse error: unexpected token '(' (Sym_paren_l).
name: variable_multiple_assignmentsdescription: Variable multiple assignments testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') int v;
name: variable_mixed_assignmentsdescription: Variable mixed assignments testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int v;
name: variable_redeclaredescription: Variable redeclaration testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_redeclare.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_redeclare.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_redeclare.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: variable_assignmentdescription: Variable assignment testsshould_fail: 0tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_assignment.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') int v;
name: variable_multiple_assignmentsdescription: Variable multiple assignments testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_multiple_assignments.sv:11: error: Unresolved net/uwire v cannot have multiple drivers.1 error(s) during elaboration.
name: variable_mixed_assignmentsdescription: Variable mixed assignments testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_mixed_assignments.sv:12: error: v Unable to assign to unresolved wires.Elaboration failed
name: variable_redeclaredescription: Variable redeclaration testsshould_fail: 1tags: 6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_redeclare.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.5--variable_redeclare.sv:9: error: duplicate declaration for net or variable 'v' in 'top'.
name: net_tridescription: tri net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_wiredescription: wire net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_wire.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_wire.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: net_tridescription: tri net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_wiredescription: wire net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_wire.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_wire.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_wire.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_tridescription: tri net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv']incdirs: []top_module: rc: 0
name: net_tridescription: tri net testshould_fail: 0tags: 6.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.1--net_tri.sv']incdirs: []top_module: rc: 0module top; tri v;endmodule
name: net_uwiredescription: uwire net testshould_fail: 0tags: 6.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.2--net_uwire.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.2--net_uwire.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_uwiredescription: uwire net testshould_fail: 0tags: 6.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.2--net_uwire.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.2--net_uwire.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.2--net_uwire.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_triordescription: trior net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv:8: Unsupported: Verilog 1995 reserved word not implemented: trior%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv
name: net_trianddescription: triand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv:8: Unsupported: Verilog 1995 reserved word not implemented: triand%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv
name: net_wanddescription: wand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv:8: Unsupported: Verilog 1995 reserved word not implemented: wand%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv
name: net_wordescription: wor net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv:8: Unsupported: Verilog 1995 reserved word not implemented: wor%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv
name: net_triordescription: trior net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_trianddescription: triand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_wanddescription: wand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_wordescription: wor net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_triordescription: trior net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_trior.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_trianddescription: triand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_triand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_wanddescription: wand net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_wordescription: wor net testshould_fail: 0tags: 6.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.3--net_wor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_triregdescription: trireg net testshould_fail: 0tags: 6.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv:8: Unsupported: Verilog 1995 reserved word not implemented: trireg%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv
name: net_triregdescription: trireg net testshould_fail: 0tags: 6.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_triregdescription: trireg net testshould_fail: 0tags: 6.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_triregdescription: trireg net testshould_fail: 0tags: 6.6.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.4--net_trireg.sv:8: sorry: trireg nets not supported.
name: net_tri1description: tri1 net testshould_fail: 0tags: 6.6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri1.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri1.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_tri0description: tri0 net testshould_fail: 0tags: 6.6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri0.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri0.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: net_tri1description: tri1 net testshould_fail: 0tags: 6.6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_tri0description: tri0 net testshould_fail: 0tags: 6.6.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.5--net_tri0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: net_supply0description: supply0 net testshould_fail: 0tags: 6.6.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: net_supply1description: supply1 net testshould_fail: 0tags: 6.6.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: net_supply0description: supply0 net testshould_fail: 0tags: 6.6.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv::8 Unsuported tokensupply0 v; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply0.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#')supply0 v;
name: net_supply1description: supply1 net testshould_fail: 0tags: 6.6.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv::8 Unsuported tokensupply1 v; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/nets/6.6.6--net_supply1.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#')supply1 v;
name: nettype_resolution_fndescription: user-defined nettype with resolution function testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:8:53: error: dimension requires a constant range function automatic real real_sum (input real driver[]); ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:10:3: error: language feature not yet supported foreach (driver[i]) ^~~~~~~~~~~~~~~~~~~
name: nettype_resolution_fndescription: user-defined nettype with resolution function testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:8: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:14: Unsupported: SystemVerilog 2012 reserved word not implemented: nettype%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:7: ../V3ParseSym.h:112: Symbols suggest ending FUNC 'real_sum' but parser thinks ending MODULE 'top'%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv
name: nettypedescription: user-defined nettype testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv:8: Unsupported: SystemVerilog 2012 reserved word not implemented: nettype%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv
name: nettype_resolution_fndescription: user-defined nettype with resolution function testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:8: syntax error, unexpected TOK_REAL, expecting ';' or '('
name: nettype_resolution_fndescription: user-defined nettype with resolution function testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function automatic real real_sum (input real driver[]);
name: nettypedescription: user-defined nettype testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') nettype real real_net;
name: nettype_resolution_fndescription: user-defined nettype with resolution function testsshould_fail: 0tags: 6.6.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.7--nettype_resolution_fn.sv:14: error: invalid module item.
name: interconnectdescription: generic interconnect testsshould_fail: 0tags: 6.6.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.8--interconnect.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.8--interconnect.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.8--interconnect.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.6.8--interconnect.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') interconnect bus;
name: logic_vectordescription: logic vector testsshould_fail: 0tags: 6.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.9.1--logic_vector.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.9.1--logic_vector.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.9.1--logic_vector.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.9.1--logic_vector.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#') logic [15:0] a;
name: implicit_portdescription: implicit port signal testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv']incdirs: []top_module: rc: 0
name: implicit_continuous_assignmentdescription: implicit declaration in continuous assignment testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv']incdirs: []top_module: rc: 0%Warning-IMPLICIT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv:11: Signal definition not found, creating implicitly: c%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
name: implicit_port_connectiondescription: implicit port connection testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv']incdirs: []top_module: rc: 0%Warning-IMPLICIT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv:12: Signal definition not found, creating implicitly: c%Warning-IMPLICIT: Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
name: implicit_portdescription: implicit port signal testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: implicit_continuous_assignmentdescription: implicit declaration in continuous assignment testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv' to AST representation.Generating RTLIL representation for module `\top'.Warning: Identifier `\c' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv:11.Successfully finished Verilog frontend.
name: implicit_port_connectiondescription: implicit port connection testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv' to AST representation.Generating RTLIL representation for module `\top'.Warning: Identifier `\c' is implicitly declared at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv:12.Generating RTLIL representation for module `\test'.Successfully finished Verilog frontend.
name: implicit_portdescription: implicit port signal testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv']incdirs: []top_module: rc: 0--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }--------------------------------------------------------------------Welcome to ODIN II version 0.1 - the better High level synthesis tools++ targetting FPGAs (mainly VPR)Email: jamieson.peter@gmail.com and ken@unb.ca for support issues--------------------------------------------------------------------High-level synthesis BeginParser starting - we'll create an abstract syntax tree. Note this tree can be viewed using Grap Viz (see documentation)Adding file /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv to parse listOptimizing module by AST based optimizationsConverting AST into a Netlist. Note this netlist can be viewed using GraphViz (see documentation)==========================Detected Top Level Module: top==========================Performing Optimizations of the NetlistPerforming Partial Map to target deviceOutputting the netlist to the specified output formatSuccessful High-level synthesis by Odin Blif file available at odin.blif Ran in 0.6ms----------------------------------------------------------------------------------------------------------------------------------------Odin ran with exit status: 0Odin II took 0.00 seconds (max_rss 6.9 MiB)
name: implicit_continuous_assignmentdescription: implicit declaration in continuous assignment testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: implicit_port_connectiondescription: implicit port connection testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: implicit_portdescription: implicit port signal testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv']incdirs: []top_module: rc: 0
name: implicit_portdescription: implicit port signal testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port.sv']incdirs: []top_module: rc: 0module top ( a, b); input [3:0] a; input [3:0] b; wire [3:0] c; assign c = (a | b);endmodule
name: implicit_continuous_assignmentdescription: implicit declaration in continuous assignment testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_continuous_assignment.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 8; wire [3:0] b = 5; assign c = (| (a | b));endmodule
name: implicit_port_connectiondescription: implicit port connection testsshould_fail: 0tags: 6.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.10--implicit_port_connection.sv']incdirs: []top_module: rc: 0module top; wire a = 1; wire b = 0; wire d; test mod( a, b, c ); assign d = c;endmodulemodule test ( a, b, c); input a; input b; output c; assign c = (a | b);endmodule
name: integer_signed_shortintdescription: signed shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv:8:1: error: expected membersigned shortint v;^~~~~~
name: integer_bitdescription: bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv']incdirs: []top_module: rc: 0
name: integer_signed_timedescription: signed time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv:8:1: error: expected membersigned time v;^~~~~~
name: integer_unsigned_intdescription: unsigned int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv:8:1: error: expected memberunsigned int v;^~~~~~~~
name: integer_timedescription: time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv']incdirs: []top_module: rc: 0
name: integer_unsigned_timedescription: unsigned time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv:8:1: error: expected memberunsigned time v;^~~~~~~~
name: integer_signed_regdescription: signed reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv:8:1: error: expected membersigned reg v;^~~~~~
name: integer_signed_bitdescription: signed bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv:8:1: error: expected membersigned bit v;^~~~~~
name: integer_signed_logicdescription: signed logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv:8:1: error: expected membersigned logic v;^~~~~~
name: integer_signed_intdescription: signed int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv:8:1: error: expected membersigned int v;^~~~~~
name: integer_signed_bytedescription: signed byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv:8: syntax error, unexpected signed%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv
name: integer_logicdescription: logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_signed_shortintdescription: signed shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv:8: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: integer_bitdescription: bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_signed_timedescription: signed time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv:8: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: integer_unsigned_intdescription: unsigned int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: integer_timedescription: time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: integer_unsigned_timedescription: unsigned time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: integer_signed_regdescription: signed reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_unsigned_integerdescription: unsigned integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv:8: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '#'
name: integer_signed_bitdescription: signed bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_signed_logicdescription: signed logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_unsigned_regdescription: unsigned reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv:8: syntax error, unexpected TOK_REG, expecting TOK_ID or '#'
name: integer_longintdescription: longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: integer_unsigned_bitdescription: unsigned bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv:8: syntax error, unexpected TOK_REG, expecting TOK_ID or '#'
name: integer_shortintdescription: shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: integer_signed_integerdescription: signed integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_intdescription: int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: integer_unsigned_bytedescription: unsigned byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: integer_unsigned_logicdescription: unsigned logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv:8: syntax error, unexpected TOK_REG, expecting TOK_ID or '#'
name: integer_unsigned_shortintdescription: unsigned shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: integer_regdescription: reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_reg.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_reg.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_signed_intdescription: signed int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv:8: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: integer_unsigned_longintdescription: unsigned longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: integer_signed_longintdescription: signed longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv:8: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: integer_integerdescription: integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_integer.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_integer.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: integer_bytedescription: byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: integer_signed_bytedescription: signed byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv:8: syntax error, unexpected TOK_ID, expecting ',' or '=' or ';' or '['
name: integer_logicdescription: logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_logic.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')logic v;
name: integer_signed_shortintdescription: signed shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed shortint v;
name: integer_bitdescription: bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')bit v;
name: integer_signed_timedescription: signed time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed time v;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv::8 Unsuported tokensigned time v; ^~~~
name: integer_unsigned_intdescription: unsigned int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned int v;
name: integer_timedescription: time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv::8 Unsuported tokentime v; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#')time v;
name: integer_unsigned_timedescription: unsigned time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv::8 Unsuported tokenunsigned time v; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')unsigned time v;
name: integer_signed_regdescription: signed reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed reg v;
name: integer_unsigned_integerdescription: unsigned integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv::8 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or '#')unsigned integer v;
name: integer_signed_bitdescription: signed bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed bit v;
name: integer_signed_logicdescription: signed logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed logic v;
name: integer_unsigned_regdescription: unsigned reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv::8 error in parsing: (syntax error, unexpected netREG, expecting vSYMBOL_ID or '#')unsigned reg v;
name: integer_longintdescription: longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')longint v;
name: integer_unsigned_bitdescription: unsigned bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned bit v;
name: integer_shortintdescription: shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')shortint v;
name: integer_signed_integerdescription: signed integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed integer v;
name: integer_intdescription: int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')int v;
name: integer_unsigned_bytedescription: unsigned byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned byte v;
name: integer_unsigned_logicdescription: unsigned logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned logic v;
name: integer_unsigned_shortintdescription: unsigned shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned shortint v;
name: integer_regdescription: reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_reg.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_reg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_reg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: integer_signed_intdescription: signed int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed int v;
name: integer_unsigned_longintdescription: unsigned longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')unsigned longint v;
name: integer_signed_longintdescription: signed longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed longint v;
name: integer_integerdescription: integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_integer.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_integer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_integer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: integer_bytedescription: byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_byte.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')byte v;
name: integer_signed_bytedescription: signed byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_byte.sv::8 error in parsing: (syntax error, unexpected vSIGNED)signed byte v;
name: integer_signed_shortintdescription: signed shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_shortint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType shortint,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_bitdescription: bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_bit.sv']incdirs: []top_module: rc: 0module top; wire v;endmodule
name: integer_signed_timedescription: signed time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_time.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType time,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_intdescription: unsigned int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_int.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType int,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_timedescription: time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_time.sv']incdirs: []top_module: rc: 0module top; time v;endmodule
name: integer_unsigned_timedescription: unsigned time net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_time.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType time,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_signed_regdescription: signed reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_reg.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType reg,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_integerdescription: unsigned integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_integer.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType integer,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_signed_bitdescription: signed bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_bit.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType bit,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_signed_logicdescription: signed logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_logic.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType logic,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_regdescription: unsigned reg net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_reg.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType reg,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_longintdescription: longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_longint.sv']incdirs: []top_module: rc: 0module top; wire signed [63:0] v;endmodule
name: integer_unsigned_bitdescription: unsigned bit net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_bit.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType bit,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_shortintdescription: shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_shortint.sv']incdirs: []top_module: rc: 0module top; wire signed [15:0] v;endmodule
name: integer_signed_integerdescription: signed integer net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_integer.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType integer,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_intdescription: int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_int.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] v;endmodule
name: integer_unsigned_bytedescription: unsigned byte net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_byte.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType byte,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_logicdescription: unsigned logic net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_logic.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType logic,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_shortintdescription: unsigned shortint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_shortint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType shortint,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_signed_intdescription: signed int net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_int.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType int,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_unsigned_longintdescription: unsigned longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_unsigned_longint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType longint,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: integer_signed_longintdescription: signed longint net testshould_fail: 0tags: 6.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/integers/6.11--integer_signed_longint.sv']incdirs: []top_module: rc: 1zachjs-sv2v: takeIdent didn't find identifier: [DTType longint,DTIdent "v"]CallStack (from HasCallStack): error, called at src/Language/SystemVerilog/Parser/ParseDecl.hs:398:20 in main:Language.SystemVerilog.Parser.ParseDecl
name: realdescription: real type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv']incdirs: []top_module: rc: 0
name: real_edgedescription: real edge event testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv:9:19: error: expression must be integral always @(posedge a) ^
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv:12:15: error: expression must be integral assign c = b[a]; ^
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11:15: error: value of type 'real' cannot be indexed assign b = a[2]; ~~^~
name: realdescription: real type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv']incdirs: []top_module: rc: 0
name: real_edgedescription: real edge event testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv:9: Unsupported: Non-single bit wide signal pos/negedge sensitivity: top.a%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv:8: Unsupported: Clock edge on non-single bit signal: top.a%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: 10%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv:12: Bit extraction of var[3:0] requires 2 bit index, not 64 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv:12: Operator SEL expected non-complex non-double Extract Range in width check%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11: Illegal bit or array select; type does not have a bit range, or bad dimension: type is real%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11: Expected integral (non-real) input to SEL%Warning-REALCVT: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11: Implicit conversion of real to integer%Warning-REALCVT: Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message.%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv
name: shortrealdescription: shortreal type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: shortreal%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv:8: syntax error, unexpected '=', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv
name: realtimedescription: realtime type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv:8: syntax error, unexpected '=', expecting '(' or '['
name: realdescription: real type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv:8: syntax error, unexpected TOK_REAL
name: real_edgedescription: real edge event testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv:8: syntax error, unexpected TOK_REAL
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv:8: syntax error, unexpected TOK_REAL
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:8: syntax error, unexpected TOK_REAL
name: shortrealdescription: shortreal type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv:8: syntax error, unexpected '=', expecting '(' or '['
name: realtimedescription: realtime type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') realtime a = 0.5;
name: realdescription: real type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') real a = 0.5;
name: real_edgedescription: real edge event testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') real a = 0.5;
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') real a = 0.5;
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') real a = 0.5;
name: shortrealdescription: shortreal type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') shortreal a = 0.5;
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: 0
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11: error: can not select part of real: a/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv:11: error: Unable to elaborate r-value: a['sd2]2 error(s) during elaboration.
name: realtimedescription: realtime type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--realtime.sv']incdirs: []top_module: rc: 0module top; realtime a = 0.5;endmodule
name: realdescription: real type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real.sv']incdirs: []top_module: rc: 0module top; real a = 0.5;endmodule
name: real_edgedescription: real edge event testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_edge.sv']incdirs: []top_module: rc: 0module top; real a = 0.5; always @(posedge a) $display("posedge");endmodule
name: real_bit_selectdescription: real bit select testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select_idx.sv']incdirs: []top_module: rc: 0module top; real a = 0.5; wire [3:0] b; wire c; assign c = b[a];endmodule
name: real_idxdescription: real indexing testsshould_fail: 1tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--real_bit_select.sv']incdirs: []top_module: rc: 0module top; real a = 0.5; wire b; assign b = a[2];endmodule
name: shortrealdescription: shortreal type testsshould_fail: 0tags: 6.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.12--shortreal.sv']incdirs: []top_module: rc: 0module top; shortreal a = 0.5;endmodule
name: voiddescription: void type testsshould_fail: 0tags: 6.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: voiddescription: void type testsshould_fail: 0tags: 6.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv::10 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: voiddescription: void type testsshould_fail: 0tags: 6.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv:13: warning: User function 'fun' is being called as a task./home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.13--void.sv:13: assert: elab_expr.cc:1264: failed assertion 0Aborted (core dumped)
name: chandledescription: chandle type testsshould_fail: 0tags: 6.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: chandledescription: chandle type testsshould_fail: 0tags: 6.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.14--chandle.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') chandle a;
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7:1: error: language feature not yet supportedvirtual class Foo; endclass^~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7:1: error: language feature not yet supportedclass macros_as_class_item;^~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:8:2: error: unknown macro or compiler directive '`moobar' `moobar(,) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:9:2: error: unknown macro or compiler directive '`zoobar' `zoobar( , ) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:10:2: error: unknown macro or compiler directive '`zootar' `zootar(12,) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:11:2: error: unknown macro or compiler directive '`zoojar' `zoojar(,34) ^
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv:7:15: error: forward typedef 'myclass_fwd' does not resolve to a data typetypedef class myclass_fwd; ^
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7:1: error: language feature not yet supportedclass Foo #(T=int);^~~~~~~~~~~~~~~~~~~
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7:1: error: language feature not yet supportedclass Foo extends Package::Bar; endclass^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7:1: error: language feature not yet supportedclass zzxx;^~~~~~~~~~~
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7:1: error: language feature not yet supportedclass Foo #(type IFType=virtual x_if);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7:1: error: language feature not yet supportedclass foo;^~~~~~~~~~
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv
name: class_test_29description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv
name: class_test_12description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected ')', expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv
name: class_test_16description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv
name: class_test_61description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv
name: class_test_11description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv
name: class_test_60description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv
name: class_test_55description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv
name: class_test_41description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:8: Define or directive not defined: `uvm_object_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:9: Define or directive not defined: `uvm_object_registry%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:10: Define or directive not defined: `uvm_sweets%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:11: Define or directive not defined: `non_uvm_macro%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:11: Define or directive not defined: `banana%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv
name: class_test_68description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv
name: class_test_56description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv
name: class_test_20description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:8: Define or directive not defined: `moobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:9: Define or directive not defined: `zoobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:10: Define or directive not defined: `zootar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:11: Define or directive not defined: `zoojar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax error, unexpected '#', expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv
name: class_test_0description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv
name: class_test_23description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv
name: class_test_64description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv
name: class_test_24description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv
name: class_test_43description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:8: Define or directive not defined: `uvm_object_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:10: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:12: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv
name: class_test_10description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: syntax error, unexpected ')', expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv
name: class_test_58description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:8: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv
name: class_test_42description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:8: Define or directive not defined: `uvm_object_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:9: Define or directive not defined: `uvm_object_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:10: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv
name: class_test_25description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv
name: class_test_53description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:11: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:11: Perhaps 'mypkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:12: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv
name: class_test_3description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv
name: class_test_28description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv
name: class_test_6description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv
name: class_test_49description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:10: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:10: Perhaps 'glb' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv
name: class_test_50description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv
name: class_test_66description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv
name: class_test_52description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv
name: class_test_18description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv
name: class_test_13description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: syntax error, unexpected type, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv
name: class_test_44description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:8: Define or directive not defined: `uvm_field_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:10: Define or directive not defined: `uvm_field_real%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:12: Define or directive not defined: `uvm_field_object%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:13: Define or directive not defined: `uvm_field_event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:14: Define or directive not defined: `uvm_field_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:15: Define or directive not defined: `uvm_field_array_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:16: Define or directive not defined: `uvm_field_sarray_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:17: Define or directive not defined: `uvm_field_aa_int_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:18: Define or directive not defined: `uvm_field_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv
name: class_test_8description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv
name: class_test_21description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: Define or directive not defined: `moobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:9: Define or directive not defined: `zoobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:10: Define or directive not defined: `zootar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: Perhaps 'dbg_pkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv
name: class_test_22description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv
name: class_test_19description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv
name: class_test_47description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:8: Define or directive not defined: `uvm_new_func%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:9: Define or directive not defined: `uvm_new_func2%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:10: Define or directive not defined: `uvm_new_func3%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv
name: class_test_26description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv
name: class_test_2description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: Perhaps 'dbg_pkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv
name: class_test_9description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv
name: class_test_15description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv
name: class_test_46description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:8: Define or directive not defined: `uvm_component_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:9: Define or directive not defined: `uvm_component_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:10: Define or directive not defined: `uvm_field_object%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:11: Define or directive not defined: `uvm_field_event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:12: Define or directive not defined: `uvm_field_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:13: Define or directive not defined: `uvm_component_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 9 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv
name: class_test_37description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv
name: class_test_45description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:8: Define or directive not defined: `uvm_object_param_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:10: Define or directive not defined: `uvm_field_real%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:12: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv
name: class_test_1description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv
name: class_test_5description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv
name: class_test_57description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv
name: class_test_35description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:10: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv
name: class_test_67description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv
name: class_test_27description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv
name: class_test_40description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:8: Define or directive not defined: `uvm_object_registry%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv
name: class_test_51description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class event_calendar;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_29description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Base implements Pkg::Bar, Baz; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_12description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N=1, int P=2) extends Bar #(x,y,z);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_16description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(IFType=virtual x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_61description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_11description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N, int P);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_60description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_55description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Driver;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_41description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_68description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_56description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Driver;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_20description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(.v1(x),.v2(y)); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef class myclass_fwd;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(T=int);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type IFType=virtual x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class foo;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_0description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class semicolon_classy; ; ;;; ; ; ;endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_23description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_64description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_24description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar, Blah, Baz; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_43description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_10description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N, P);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_58description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class fields_with_modifiers;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_42description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_25description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Package::Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_53description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class param_types_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_3description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class automatic Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_28description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Base implements Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_6description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_49description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class params_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_50description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class params_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_66description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_52description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class how_wide #(type DT=int) extends uvm_sequence_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_18description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type IFType=virtual interface x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_13description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int W=8, type Int=int) extends Bar #(x,y,z);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_44description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_8description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_21description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxy;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_22description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(.v1(x),.v2(y)); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_19description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_47description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_id_as_call;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_26description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar#(N); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_2description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class static Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzyyy;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_9description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_15description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type KeyType=int, Int=int);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_46description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_37description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class foo extends bar;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_45description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_1description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_5description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class automatic Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_57description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class fields_with_modifiers;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_35description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_67description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_27description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Package::Bar#(1, 2); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_40description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_51description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class how_wide;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: error: invalid class item.
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: error: Error in task/function port item after port name analysis_port./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax errorI give up.
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: warning: macro moobar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:9: warning: macro zoobar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:10: warning: macro zootar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: syntax errorI give up.
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: error: Error in task/function port item after port name dbg_pkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax errorI give up.
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: error: Error in task/function port item after port name dbg_pkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax errorI give up.
name: stringdescription: string type testsshould_fail: 0tags: 6.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: stringdescription: string type testsshould_fail: 0tags: 6.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16--string.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: string_lendescription: string.len() testsshould_fail: 0tags: 6.16.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv:9:11: error: invalid member access for type 'string' int b = a.len(); ~^~~~
name: string_lendescription: string.len() testsshould_fail: 0tags: 6.16.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv
name: string_lendescription: string.len() testsshould_fail: 0tags: 6.16.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int b = a.len();
name: string_lendescription: string.len() testsshould_fail: 0tags: 6.16.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv:9: error: The RHS expression must be constant./home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.1--string_len.sv:9 : This expression violates the rule: $ivl_string_method$len(a)Elaboration failed
name: string_putcdescription: string.putc() testsshould_fail: 0tags: 6.16.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.2--string_putc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.2--string_putc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.2--string_putc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.2--string_putc.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";
name: string_getcdescription: string.getc() testsshould_fail: 0tags: 6.16.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv
name: string_getcdescription: string.getc() testsshould_fail: 0tags: 6.16.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') byte b = a.getc(2);
name: string_getcdescription: string.getc() testsshould_fail: 0tags: 6.16.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.3--string_getc.sv:9: error: No function named `a.getc' found in this context (top).Elaboration failed
name: string_toupperdescription: string.toupper() testsshould_fail: 0tags: 6.16.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv
name: string_toupperdescription: string.toupper() testsshould_fail: 0tags: 6.16.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') string b = a.toupper();
name: string_toupperdescription: string.toupper() testsshould_fail: 0tags: 6.16.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.4--string_toupper.sv:9: error: No function named `a.toupper' found in this context (top).Elaboration failed
name: string_tolowerdescription: string.tolower() testsshould_fail: 0tags: 6.16.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv
name: string_tolowerdescription: string.tolower() testsshould_fail: 0tags: 6.16.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') string b = a.tolower();
name: string_tolowerdescription: string.tolower() testsshould_fail: 0tags: 6.16.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.5--string_tolower.sv:9: error: No function named `a.tolower' found in this context (top).Elaboration failed
name: string_comparedescription: string.compare() testsshould_fail: 0tags: 6.16.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv:10:11: error: invalid member access for type 'string' int c = a.compare(b); ~^~~~~~~~
name: string_comparedescription: string.compare() testsshould_fail: 0tags: 6.16.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv:10: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv:10: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv
name: string_comparedescription: string.compare() testsshould_fail: 0tags: 6.16.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') string b = "TEST";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(') int c = a.compare(b);
name: string_comparedescription: string.compare() testsshould_fail: 0tags: 6.16.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.6--string_compare.sv:10: error: No function named `a.compare' found in this context (top).Elaboration failed
name: string_icomparedescription: string.icompare() testsshould_fail: 0tags: 6.16.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv:10:11: error: invalid member access for type 'string' int c = a.icompare(b); ~^~~~~~~~~
name: string_icomparedescription: string.icompare() testsshould_fail: 0tags: 6.16.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv:10: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv:10: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv
name: string_icomparedescription: string.icompare() testsshould_fail: 0tags: 6.16.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "Test";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') string b = "TEST";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(') int c = a.icompare(b);
name: string_icomparedescription: string.icompare() testsshould_fail: 0tags: 6.16.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.7--string_icompare.sv:10: error: No function named `a.icompare' found in this context (top).Elaboration failed
name: string_substrdescription: string.substr() testsshould_fail: 0tags: 6.16.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.8--string_substr.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.8--string_substr.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.8--string_substr.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.8--string_substr.sv
name: string_atobindescription: string.atobin() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv:9:11: error: invalid member access for type 'string' int b = a.atobin(); ~^~~~~~~
name: string_atohexdescription: string.atohex() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv:9:11: error: invalid member access for type 'string' int b = a.atohex(); ~^~~~~~~
name: string_atoidescription: string.atoi() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv:9:11: error: invalid member access for type 'string' int b = a.atoi(); ~^~~~~
name: string_atooctdescription: string.atooct() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv:9:11: error: invalid member access for type 'string' int b = a.atooct(); ~^~~~~~~
name: string_atobindescription: string.atobin() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv
name: string_atohexdescription: string.atohex() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv
name: string_atoidescription: string.atoi() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv
name: string_atooctdescription: string.atooct() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv
name: string_atobindescription: string.atobin() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "10101";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int b = a.atobin();
name: string_atohexdescription: string.atohex() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "0xff";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int b = a.atohex();
name: string_atoidescription: string.atoi() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "1234";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int b = a.atoi();
name: string_atooctdescription: string.atooct() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "777";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int b = a.atooct();
name: string_atobindescription: string.atobin() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atobin.sv:9: error: No function named `a.atobin' found in this context (top).Elaboration failed
name: string_atohexdescription: string.atohex() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atohex.sv:9: error: No function named `a.atohex' found in this context (top).Elaboration failed
name: string_atoidescription: string.atoi() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atoi.sv:9: error: No function named `a.atoi' found in this context (top).Elaboration failed
name: string_atooctdescription: string.atooct() testsshould_fail: 0tags: 6.16.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.9--string_atooct.sv:9: error: No function named `a.atooct' found in this context (top).Elaboration failed
name: string_atorealdescription: string.atoreal() testsshould_fail: 0tags: 6.16.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv:9:12: error: invalid member access for type 'string' real b = a.atoreal(); ~^~~~~~~~
name: string_atorealdescription: string.atoreal() testsshould_fail: 0tags: 6.16.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv:9: Unsupported: Member call on non-enum object 'VARREF 'a'' which is a 'BASICDTYPE 'string''%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv:9: ../V3Width.cpp:3104: Node has no type%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv
name: string_atorealdescription: string.atoreal() testsshould_fail: 0tags: 6.16.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') string a = "4.76";PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') real b = a.atoreal();
name: string_atorealdescription: string.atoreal() testsshould_fail: 0tags: 6.16.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.10--string_atoreal.sv:9: error: No function named `a.atoreal' found in this context (top).Elaboration failed
name: string_itoadescription: string.itoa() testsshould_fail: 0tags: 6.16.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.11--string_itoa.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.11--string_itoa.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.11--string_itoa.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.11--string_itoa.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: string_hextoadescription: string.hextoa() testsshould_fail: 0tags: 6.16.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.12--string_hextoa.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.12--string_hextoa.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.12--string_hextoa.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.12--string_hextoa.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: string_octtoadescription: string.octtoa() testsshould_fail: 0tags: 6.16.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.13--string_octtoa.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.13--string_octtoa.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.13--string_octtoa.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.13--string_octtoa.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: string_bintoadescription: string.bintoa() testsshould_fail: 0tags: 6.16.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.14--string_bintoa.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.14--string_bintoa.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.14--string_bintoa.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.14--string_bintoa.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: string_realtoadescription: string.realtoa() testsshould_fail: 0tags: 6.16.15files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.15--string_realtoa.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.15--string_realtoa.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.15--string_realtoa.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.16.15--string_realtoa.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') string a;
name: eventdescription: event type testsshould_fail: 0tags: 6.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv:8: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv
name: eventdescription: event type testsshould_fail: 0tags: 6.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: eventdescription: event type testsshould_fail: 0tags: 6.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv::8 Unsuported token event a; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.17--event.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') event a;
name: typedefdescription: user types testsshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv:8:9: error: expected identifier typedef wire wire_t; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv:8:10: error: expected data type (implicit type name not allowed) typedef wire wire_t; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv:10:2: error: 'wire_t' is not a type wire_t a; ^~~~~~
name: typedef_test_15description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv:8:9: error: expected data type (implicit type name not allowed) [4:0] some_member; ^
name: typedef_test_12description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv:7:9: error: use of undeclared identifier 'data_t'typedef data_t my_array_t [bit[31:0]]; ^~~~~~
name: typedef_test_26description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv:11:12: error: expression width of 4 does not exactly match declared enum type width of 32 Global = 4'h1, ^~~~
name: typedef_test_27description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv:8:12: error: expression width of 4 does not exactly match declared enum type width of 32 Global = 4'h2, ^~~~
name: typedef_test_19description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv:8:12: error: expression width of 4 does not exactly match declared enum type width of 1 Global = 4'h2, ^~~~
name: typedef_test_0description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv:7:9: error: forward typedef 'i_am_a_type_really' does not resolve to a data typetypedef i_am_a_type_really; ^
name: typedef_test_11description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv:7:9: error: use of undeclared identifier 'data_t'typedef data_t my_array_t [bit]; ^~~~~~
name: typedef_test_17description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv:8:3: error: unknown class or package 'apkg' apkg::type_member #(N, M) [P:0] some_member; ^~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv:8:28: error: expected declarator apkg::type_member #(N, M) [P:0] some_member; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv:8:30: error: use of undeclared identifier 'P' apkg::type_member #(N, M) [P:0] some_member; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv:8:35: error: expected data type (implicit type name not allowed) apkg::type_member #(N, M) [P:0] some_member; ^
name: typedef_test_22description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv:7:14: error: use of undeclared identifier 'uvec8_t'typedef enum uvec8_t { ^~~~~~~
name: typedef_test_21description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv:7:14: error: invalid enum base type 'bit[3:0][7:0]' (must be a single dimensional integer type)typedef enum bit[3:0][7:0] { ^
name: typedef_test_24description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv']incdirs: []top_module: rc: 10%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv:7: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv
name: typedef_test_23description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv:7: syntax error, unexpected ::, expecting '{'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv:7: Perhaps 'yourpkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv
name: typedef_test_1description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv
name: typedef_test_18description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv:9: Unsupported: Unpacked array in packed struct/union%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv
name: typedef_test_25description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv:8: Can't find definition of variable: A%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv:9: Can't find definition of variable: D%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv:11: Can't find definition of variable: E%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv:13: Can't find definition of variable: M%Error: Exiting due to 4 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv
name: typedef_test_2description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv
name: typedef_test_20description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv
name: typedef_test_19description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv
name: typedef_test_0description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv
name: typedefdescription: user types testsshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv::8 error in parsing: (syntax error, unexpected netWIRE, expecting vSYMBOL_ID or '#') typedef wire wire_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.18--typedef.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(') wire_t a;
name: typedef_test_15description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_15.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct packed {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_24description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_24.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_5description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef union { int i; bool b; } bint;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_4description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum { RED, GREEN, BLUE } colors;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_3description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef reg[1:0] quartet[1:0];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_12description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_12.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef data_t my_array_t [bit[31:0]];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_26description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_26.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_27description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_27.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_6description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct { int i; bool b; } mystruct;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_23description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_23.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum yourpkg::num_t {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_1description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef reg[3:0] quartet;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_18description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_18.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_25description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_25.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct packed {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_2description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef reg quartet[3:0];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_20description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_20.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum logic[3:0] {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_19description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_19.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum logic {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_0description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef i_am_a_type_really;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_11description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef data_t my_array_t [bit];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_7description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct { int i, j, k; bool b, c, d; } mystruct;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_17description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_17.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct packed {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_22description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_22.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum uvec8_t {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_21description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_21.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum bit[3:0][7:0] {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_10description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef data_t my_array_t [ * ];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_14description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_14.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef some_package::some_type myalias;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_13description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_13.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef data_t my_ar_t [bit[31:0][k:0]][bit[j:0][l:0]];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_8description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef some_other_type myalias;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_16description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_16.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct packed {ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: typedef_test_9description: Testshould_fail: 0tags: 6.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/typedef/typedef_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef data_t my_array_t [k:0][j:0];ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv:8:35: error: cannot increment previous value 32'sbxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx because it has unknown bits enum integer {a=0, b={32{1'bx}}, c} val; ~~~~~~~~~~ ^
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv:8:25: error: redefinition of enum value 2'b0 enum bit [1:0] {a=0, b=2'bxx, c=1} val; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv:8:20: note: previous definition here enum bit [1:0] {a=0, b=2'bxx, c=1} val; ^
name: enum_test_0description: Testshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv:7:14: error: forward typedef 'myenum_fwd' does not resolve to a data typetypedef enum myenum_fwd; ^
name: enum_xxdescription: enum with x testsshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv']incdirs: []top_module: rc: 0
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: 0
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: 0
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: 0
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: 0
name: enum_test_0description: Testshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv
name: enum_xxdescription: enum with x testsshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv:8: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '#'
name: enum_xxdescription: enum with x testsshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv::8 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or '#') enum integer {a=0, b={32{1'bx}}, c=1} val;
name: enum_anondescription: anonymous enum testsshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_anon.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_anon.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_anon.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_anon.sv::8 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#') enum {a, b, c} val;
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv::8 error in parsing: (syntax error, unexpected vINTEGER, expecting vSYMBOL_ID or '#') enum integer {a=0, b={32{1'bx}}, c} val;
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') enum bit [1:0] {a=0, b=2'bxx, c=1} val;
name: enum_test_0description: Testshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/enum/enum_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef enum myenum_fwd;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_xxdescription: enum with x testsshould_fail: 0tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx.sv']incdirs: []top_module: rc: 0
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv:8: error: Enumeration name c has an undefined inferred value.2 error(s) during elaboration.
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv:8: error: Enumeration name b can not have an undefined value.2 error(s) during elaboration.
name: enum_xx_inv_orderdescription: unassigned name following enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv_order.sv']incdirs: []top_module: rc: 0module top; integer val;endmodule
name: enum_xx_invdescription: invalid enum with x testsshould_fail: 1tags: 6.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19--enum_xx_inv.sv']incdirs: []top_module: rc: 0module top; wire [1:0] val;endmodule
name: enum_sequence_rangedescription: enum sequence range testsshould_fail: 0tags: 6.19.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence_range.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence_range.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence_range.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence_range.sv::8 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#') enum {start=10, stop[11:13]} e;
name: enum_sequencedescription: enum sequence testsshould_fail: 0tags: 6.19.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.2--enum_sequence.sv::8 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#') enum {start=10, step[10]} e;
name: enum_type_checking_invdescription: invalid enum assignment testsshould_fail: 1tags: 6.19.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv:12:7: error: no implicit conversion from 'int' to 'top.e'; explicit conversion exists, are you missing a cast? val = 1; ~~~ ^ ~
name: enum_type_checkingdescription: enum type checking testsshould_fail: 0tags: 6.19.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_type_checking_invdescription: invalid enum assignment testsshould_fail: 1tags: 6.19.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.3--enum_type_checking_inv.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_numerical_expr_no_castdescription: enum numerical expression without castingshould_fail: 1tags: 6.19.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv:13:7: error: no implicit conversion from 'int' to 'top.e'; explicit conversion exists, are you missing a cast? val += 1; ~~~ ^ ~
name: enum_numerical_expr_no_castdescription: enum numerical expression without castingshould_fail: 1tags: 6.19.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_no_cast.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_numerical_expr_castdescription: enum numerical expression with castingshould_fail: 0tags: 6.19.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr_cast.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_numerical_exprdescription: enum numerical expression testsshould_fail: 0tags: 6.19.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv::11 error in parsing: (syntax error, unexpected vINTEGER) integer i;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.4--enum_numerical_expr.sv::12 error in parsing: (syntax error, unexpected ';', expecting '(') e val;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_firstdescription: enum first method testsshould_fail: 0tags: 6.19.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: enum_firstdescription: enum first method testsshould_fail: 0tags: 6.19.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.1--enum_first.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = a;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_lastdescription: enum last method testsshould_fail: 0tags: 6.19.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: enum_lastdescription: enum last method testsshould_fail: 0tags: 6.19.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.2--enum_last.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = a;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_nextdescription: enum next method testsshould_fail: 0tags: 6.19.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: enum_nextdescription: enum next method testsshould_fail: 0tags: 6.19.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.3--enum_next.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = a;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_prevdescription: enum prev method testsshould_fail: 0tags: 6.19.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.4--enum_prev.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.4--enum_prev.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.4--enum_prev.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.4--enum_prev.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.4--enum_prev.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = b;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_numdescription: enum num method testsshould_fail: 0tags: 6.19.5.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: enum_numdescription: enum num method testsshould_fail: 0tags: 6.19.5.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv::12 error in parsing: (syntax error, unexpected '=', expecting '(') int n = val.num();ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_numdescription: enum num method testsshould_fail: 0tags: 6.19.5.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.5--enum_num.sv:13: syntax errorI give up.
name: enum_namedescription: enum name method testsshould_fail: 0tags: 6.19.5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: enum_namedescription: enum name method testsshould_fail: 0tags: 6.19.5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {a, b, c, d} e;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') e val = a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv::12 error in parsing: (syntax error, unexpected '=', expecting '(') string s = val.name();ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: enum_namedescription: enum name method testsshould_fail: 0tags: 6.19.5.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.19.5.6--enum_name.sv:13: syntax errorI give up.
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0
name: parameter_aggregatedescription: parameter aggregate type testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv:8:35: error: language feature not yet supported parameter logic [31:0] p [3:0] = '{1, 2, 3, 4}; ^~~~~~~~~~~~~
name: parameter_port_listdescription: parameter port list testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv']incdirs: []top_module: rc: 0
name: parameter_depdescription: parameter depending on another parameter testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_dep.sv']incdirs: []top_module: rc: 0
name: parameter_rangedescription: parameter with implied range testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_range.sv']incdirs: []top_module: rc: 0
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: parameter_aggregatedescription: parameter aggregate type testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv:8: syntax error, unexpected TOK_REG
name: parameter_port_listdescription: parameter port list testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv:7: syntax error
name: parameter_depdescription: parameter depending on another parameter testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_dep.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_dep.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_dep.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: parameter_rangedescription: parameter with implied range testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_range.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_range.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_range.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: parameterdescription: parameter testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv::8 error in parsing: (syntax error, unexpected '.', expecting ';' or ',') parameter p = 4.76;
name: parameter_aggregatedescription: parameter aggregate type testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv::8 error in parsing: (syntax error, unexpected '[', expecting ';' or ',') parameter logic [31:0] p [3:0] = '{1, 2, 3, 4};
name: parameter_port_listdescription: parameter port list testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vPARAMETER or ')')module top #(p = 12);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: parameter_depdescription: parameter depending on another parameter testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_dep.sv']incdirs: []top_module: rc: 0
name: parameter_rangedescription: parameter with implied range testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_range.sv']incdirs: []top_module: rc: 0
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0
name: parameter_aggregatedescription: parameter aggregate type testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_aggregate.sv:8: error: syntax error in parameter list.
name: parameter_port_listdescription: parameter port list testsshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_port_list.sv:7: syntax errorI give up.
name: parameter_realdescription: parameter with real value testshould_fail: 0tags: 6.20.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2--parameter_real.sv']incdirs: []top_module: rc: 0module top; parameter p = 4.76;endmodule
name: parameter_unboundeddescription: unbounded parameter $ testsshould_fail: 0tags: 6.20.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Unsupported expression on dynamic range select on signal `\a' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv:12!
name: parameter_unboundeddescription: unbounded parameter $ testsshould_fail: 0tags: 6.20.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.2.1--parameter_unbounded.sv::8 error in parsing: (syntax error, unexpected ';') parameter p = $;
name: parameter_typedescription: parameter type testsshould_fail: 0tags: 6.20.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv:7:14: error: language feature not yet supportedmodule top #(type T = real); ^~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv:7:23: error: expected expressionmodule top #(type T = real); ^~~~
name: parameter_typedescription: parameter type testsshould_fail: 0tags: 6.20.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv:7: syntax error, unexpected TOK_ID, expecting '='
name: parameter_typedescription: parameter type testsshould_fail: 0tags: 6.20.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vPARAMETER or ')')module top #(type T = real);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: parameter_typedescription: parameter type testsshould_fail: 0tags: 6.20.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.3--parameter_type.sv:7: syntax errorI give up.
name: localparamdescription: localparam testsshould_fail: 0tags: 6.20.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.4--localparam.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.4--localparam.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.4--localparam.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: specparam_invdescription: specparam assignment to param should be invalidshould_fail: 1tags: 6.20.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv']incdirs: []top_module: rc: 0
name: specparam_invdescription: specparam assignment to param should be invalidshould_fail: 1tags: 6.20.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv::8 error in parsing: (syntax error, unexpected vSPECPARAM) specparam delay = 50;
name: specparamdescription: specparam testsshould_fail: 0tags: 6.20.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam.sv::8 error in parsing: (syntax error, unexpected vSPECPARAM) specparam delay = 50;
name: specparam_invdescription: specparam assignment to param should be invalidshould_fail: 1tags: 6.20.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv']incdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv:9: warning: specparam 'delay' is being used in a constant expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.20.5--specparam_inv.sv:9: : This will prevent it being annotated at run time.
name: type_opdescription: type operator testsshould_fail: 0tags: 6.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv:10: syntax error, unexpected type, expecting IDENTIFIER or do or final%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv
name: type_opdescription: type operator testsshould_fail: 0tags: 6.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv:8: syntax error, unexpected TOK_REAL
name: type_opdescription: type operator testsshould_fail: 0tags: 6.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') real a = 4.76;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') real b = 0.74;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.23--type_op.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') var type(a+b) c;
name: cast_opdescription: cast operatorshould_fail: 0tags: 6.24.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.1--cast_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.1--cast_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.1--cast_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.1--cast_op.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') int a = int'(2.1 * 3.7);
name: cast_taskdescription: $cast taskshould_fail: 0tags: 6.24.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv:10: Unsupported or unknown PLI call: $cast%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv
name: cast_fndescription: $cast functionshould_fail: 0tags: 6.24.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv:10: Unsupported or unknown PLI call: $cast%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv
name: cast_taskdescription: $cast taskshould_fail: 0tags: 6.24.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_task.sv::10 error in parsing: (syntax error, unexpected '.', expecting ')') $cast(a, 2.1 * 3.7);
name: cast_fndescription: $cast functionshould_fail: 0tags: 6.24.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-6/6.24.2--cast_fn.sv::10 error in parsing: (syntax error, unexpected '.', expecting ')') if (! $cast(a, 2.1 * 3.7))
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: 0%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv:9: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv:9: syntax error, unexpected '{', expecting TOK_ID or '#'
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')struct packed {
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#')struct {
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: struct_test_0description: Testshould_fail: 0tags: 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv:7:16: error: forward typedef 'mystruct_fwd' does not resolve to a data typetypedef struct mystruct_fwd; ^
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: 0%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv:9: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
name: struct_test_0description: Testshould_fail: 0tags: 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv:9: syntax error, unexpected TOK_SIGNED, expecting '(' or '['
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv:9: syntax error, unexpected '{', expecting TOK_ID or '#'
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')struct packed {
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv::9 error in parsing: (syntax error, unexpected vSIGNED, expecting '(')struct packed signed {
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')struct packed unsigned {
name: basic-unpacked-structuresdescription: Test unpacked structures supportshould_fail: 0tags: 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#')struct {
name: struct_test_0description: Testshould_fail: 0tags: 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/struct/struct_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef struct mystruct_fwd;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 0
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 0
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv:9: syntax error, unexpected TOK_SIGNED, expecting '(' or '['
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: basic-packed-structuresdescription: Test packed structures supportshould_fail: 0tags: 7.2.1 7.2 7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')struct packed {
name: packed-and-signed-structuresdescription: Test packed and signed structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/signed.sv::9 error in parsing: (syntax error, unexpected vSIGNED, expecting '(')struct packed signed {
name: packed-and-unsigned-structuresdescription: Test packed and unsigned structures supportshould_fail: 0tags: 7.2.1 7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/unsigned.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')struct packed unsigned {
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv:16:15: error: packed members can not have initializers bit [3:0] lo = c; ^ ~
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: 0
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: 0
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: 255%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv:12: Unsupported: Initial values in struct/union members.%Error: Verilator internal fault, sorry. Consider trying --debug --gdbbt%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv:15: syntax error, unexpected '{', expecting '(' or '['
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv:11: syntax error, unexpected '{', expecting TOK_ID or '#'
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv::15 error in parsing: (syntax error, unexpected '{', expecting '(')struct packed {
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv::11 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#')struct {
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: 0
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv:11: sorry: Unpacked structs not supported.
name: packed-structures-default-members-valuedescription: Test packed structures default value supportshould_fail: 1tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/packed/default-value.sv:16:22: Parse error: unexpected token '=' (Sym_eq).
name: unpacked-structures-members-default-valuedescription: Test unpacked structures members default value supportshould_fail: 0tags: 7.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/structures/unpacked/default-value.sv:12:22: Parse error: unexpected token '=' (Sym_eq).
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv:9:1: error: language feature not yet supportedunion {^~~~~~~
name: union_test_0description: Testshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv:7:15: error: forward typedef 'myunion_fwd' does not resolve to a data typetypedef union myunion_fwd; ^
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: 0%Warning-UNPACKED: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv:9: Unsupported: Unpacked struct/union%Warning-UNPACKED: Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message.
name: union_test_0description: Testshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv']incdirs: []top_module: rc: 10%Error: Duplicate declaration of cell: $unit%Error: ... Location of original declaration%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv:9: syntax error, unexpected '{', expecting TOK_ID or '#'
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting vSYMBOL_ID or '#')union {
name: union_test_0description: Testshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef union myunion_fwd;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv:9: sorry: Unpacked structs not supported.
name: union_test_0description: Testshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/union/union_test_0.sv:7: sorry: Union forward declarations not supported yet.
name: basic-uniondescription: Test basic union supportshould_fail: 0tags: 7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/basic.sv']incdirs: []top_module: rc: 0module top; union { logic [7:0] v1; logic [3:0] v2; } un; initial begin un.v1 = 8'd140; $display(":assert: (%d == 140)", un.v1); $display(":assert: (%d == 12)", un.v2); endendmodule
name: basic-packed-unionsdescription: Test basic union supportshould_fail: 0tags: 7.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv:9:1: error: language feature not yet supportedunion packed {^~~~~~~~~~~~~~
name: basic-packed-unionsdescription: Test basic union supportshould_fail: 0tags: 7.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv']incdirs: []top_module: rc: 0
name: basic-packed-unionsdescription: Test basic union supportshould_fail: 0tags: 7.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: basic-packed-unionsdescription: Test basic union supportshould_fail: 0tags: 7.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')union packed {
name: basic-packed-unionsdescription: Test basic union supportshould_fail: 0tags: 7.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/packed/basic.sv']incdirs: []top_module: rc: 0
name: basic-tagged-packed-uniondescription: Test tagged packed union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:9:1: error: language feature not yet supportedunion tagged packed {^~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:15:10: error: language feature not yet supported un = tagged v2 (10); ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:15:19: error: expected ';' un = tagged v2 (10); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:15:20: error: expected statement un = tagged v2 (10); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:16:7: error: language feature not yet supported un = tagged v1 (85); // 101_0101 ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:16:16: error: expected ';' un = tagged v1 (85); // 101_0101 ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:16:17: error: expected statement un = tagged v1 (85); // 101_0101 ^
name: basic-tagged-uniondescription: Test basic tagged union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:9:1: error: language feature not yet supportedunion tagged {^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:15:7: error: language feature not yet supported un = tagged valid (10); ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:15:19: error: expected ';' un = tagged valid (10); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:15:20: error: expected statement un = tagged valid (10); ^
name: basic-tagged-packed-uniondescription: Test tagged packed union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv']incdirs: []top_module: rc: 0
name: basic-tagged-uniondescription: Test basic tagged union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv']incdirs: []top_module: rc: 0
name: basic-tagged-packed-uniondescription: Test tagged packed union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv
name: basic-tagged-uniondescription: Test basic tagged union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:10: syntax error, unexpected void, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:12: syntax error, unexpected '}'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:7: ../V3ParseSym.h:112: Symbols suggest ending UNIONDTYPE but parser thinks ending MODULE 'top'%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv
name: basic-tagged-packed-uniondescription: Test tagged packed union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: basic-tagged-uniondescription: Test basic tagged union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: basic-tagged-packed-uniondescription: Test tagged packed union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')union tagged packed {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') un = tagged v2 (10);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/packed.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: basic-tagged-uniondescription: Test basic tagged union supportshould_fail: 0tags: 7.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') un = tagged valid (10);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/unions/tagged/basic.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: basic-packeddescription: Test packed arrays supportshould_fail: 0tags: 7.4.1 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: basic-unpackeddescription: Test unpacked arrays supportshould_fail: 0tags: 7.4.2 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: basic-packeddescription: Test packed arrays supportshould_fail: 0tags: 7.4.1 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] _bit;
name: basic-unpackeddescription: Test unpacked arrays supportshould_fail: 0tags: 7.4.2 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit _bit [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')logic _logic [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::11 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')reg _reg [7:0];
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0
name: basic-packeddescription: Test packed arrays supportshould_fail: 0tags: 7.4.1 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$high' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv:12.
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$low' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv:12.
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$increment' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv:12.
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$size' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv:12.
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$unpacked_dimensions' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv:12.
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$right' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv:12.
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$dimensions' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv:12.
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$left' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv:12.
name: basic-packeddescription: Test packed arrays supportshould_fail: 0tags: 7.4.1 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] _bit;
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -11
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 0
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 0
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 0
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 0
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 0
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:9: syntax error, unexpected TOK_ID, expecting ',' or ')' or '['
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']'
name: basic-unpackeddescription: Test unpacked arrays supportshould_fail: 0tags: 7.4.2 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9: syntax error, unexpected ']'
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: syntax error, unexpected ']'
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: syntax error, unexpected ']'
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: syntax error, unexpected ']'
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: syntax error, unexpected ']'
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int A [3:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int B [0:3];
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')task fun(int a [2:0]);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::12 error in parsing: (syntax error, unexpected vENDTASK)endtask;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') int b [2:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::21 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#') fun(b);ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr[] = { 0, 1, 3, 3 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') q = arr.find with ( item == item.index );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: basic-unpackeddescription: Test unpacked arrays supportshould_fail: 0tags: 7.4.2 7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit _bit [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')logic _logic [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/basic.sv::11 error in parsing: (syntax error, unexpected '[', expecting ';' or ',')reg _reg [7:0];
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 3, 5, 7 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 4, 5, 3, 1 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') s.reverse;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 1, 2, 3, 4, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.shuffle;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 4, 5, 3, 1 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.rsort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv:18: error: Cannot assign to array B. Did you forget a word index?1 error(s) during elaboration.
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:12: error: invalid module item.
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: error: malformed statement
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:15: error: malformed statement
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:15: error: malformed statement
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:15: error: malformed statement
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd4, 'sd5, 'sd3, 'sd1}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {"hello", "sad", "world"}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd4, 'sd5, 'sd3, 'sd1}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: 0module top; reg signed [127:0] A; reg signed [127:0] B; initial begin A[0+:32] = 0; A[32+:32] = 1; A[64+:32] = 2; A[96+:32] = 3; B = A; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2) and (%d == 3))", B[0+:32], B[32+:32], B[64+:32], B[96+:32]); endendmodule
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0module top; task fun; reg signed [95:0] a; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", a[0+:32], a[32+:32], a[64+:32]); endtask initial begin : sv2v_autoblock_0 reg signed [95:0] b; b[0+:32] = 0; b[32+:32] = 1; b[64+:32] = 2; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", b[0+:32], b[32+:32], b[64+:32]); fun(b); endendmodule
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9:9: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27:11: error: value must be positive arr_b[4+:c] = arr_a[1+:c]; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27:25: error: value must be positive arr_b[4+:c] = arr_a[1+:c]; ^
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:13:10: error: language feature not yet supported arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:14:10: error: language feature not yet supported arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:13:10: error: language feature not yet supported arr_a = '{1, 1, 1, 0, 0, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:14:10: error: language feature not yet supported arr_b = '{1, 1, 1, 0, 0, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:13:10: error: language feature not yet supported arr_a = '{1, 1, 1, 1, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:14:10: error: language feature not yet supported arr_b = '{0, 0, 0, 0, 1, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:12:8: error: language feature not yet supported arr = '{0, 0, 0, 0, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:16:8: error: language feature not yet supported arr = '{1, 1, 0, 1, 1, 1, 1, 0 }; ^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:20:8: error: language feature not yet supported arr = '{1, 0, 1, 0, 1, 1, 0, 1 }; ^~~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv:13:10: error: language feature not yet supported arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv:14:10: error: language feature not yet supported arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15:10: error: language feature not yet supported arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:16:10: error: language feature not yet supported arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: Unsupported: MSB < LSB of bit extract: 3<4%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: Unsupported: MSB < LSB of bit extract: 0<1%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: 10%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:20: ../V3EmitC.cpp:758: Unknown node type reached emitter: SLICESEL%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: Illegal +: or -: select; type already selected, or bad dimension: type is UNPACKARRAYDTYPE%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv:15.
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Failed to evaluate system task `$display' with non-constant argument at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv:15.
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv:15.
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:25.
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv:15.
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv:13.
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv:15.
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv:17.
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:13: syntax error, unexpected $undefined
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:13: syntax error, unexpected $undefined
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:13: syntax error, unexpected $undefined
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:12: syntax error, unexpected $undefined
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv:13: syntax error, unexpected $undefined
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15: syntax error, unexpected $undefined
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr [7:0];
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-slice-rwdescription: Test packed arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-treat-as-integerdescription: Test packed arrays operations support (treat array as integer)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/treat-as-integer.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-equalitydescription: Test packed arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-zero-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 1tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: error: Indexed part widths must be constant and greater than zero./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: : This part width expression violates the rule: c/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: error: Indexed part widths must be constant and greater than zero./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice-zero.sv:27: : This part width expression violates the rule: c2 error(s) during elaboration.
name: operations-on-arrays-slice-equalitydescription: Test packed arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/slice-equality.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-rwdescription: Test packed arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/operations.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-one-bitdescription: Test packed arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/onebit.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-slice-rwdescription: Test unpacked arrays operations support (R&W slice)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv']incdirs: []top_module: rc: 3/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:13: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:14: error: Cannot assign to array arr_b. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice.sv:20: error: cannot perform a part select on array arr_b.3 error(s) during elaboration.
name: operations-on-arrays-equalitydescription: Test unpacked arrays operations support (equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:13: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:14: error: Cannot assign to array arr_b. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:20: error: Array arr_a needs an array index here./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:20: error: Array arr_b needs an array index here./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:21: error: Array arr_a needs an array index here./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/equality.sv:21: error: Array arr_b needs an array index here.6 error(s) during elaboration.
name: operations-on-arrays-slice-equalitydescription: Test unpacked arrays operations support (slice equality)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:13: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:14: error: Cannot assign to array arr_b. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:20: error: Array cannot be indexed by a range./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:20: error: Array cannot be indexed by a range./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:21: error: Array cannot be indexed by a range./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/slice-equality.sv:21: error: Array cannot be indexed by a range.6 error(s) during elaboration.
name: operations-on-arrays-rwdescription: Test unpacked arrays operations support (R & W)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv']incdirs: []top_module: rc: 3/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:12: error: Cannot assign to array arr. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:16: error: Cannot assign to array arr. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/operations.sv:20: error: Cannot assign to array arr. Did you forget a word index?3 error(s) during elaboration.
name: operations-on-arrays-one-bitdescription: Test unpacked arrays operations support (one bit)should_fail: 0tags: 7.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv:13: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/onebit.sv:14: error: Cannot assign to array arr_b. Did you forget a word index?2 error(s) during elaboration.
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:16: error: Cannot assign to array arr_b. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: error: Array cannot be indexed by a range./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: error: Array cannot be indexed by a range.4 error(s) during elaboration.
name: basicdescription: Test memories supportshould_fail: 0tags: 7.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: memories-read-writedescription: Test memories read-write supportshould_fail: 0tags: 7.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Failed to evaluate system task `$display' with non-constant argument at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv:15.
name: basicdescription: Test memories supportshould_fail: 0tags: 7.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/basic.sv::11 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [7:0] mem [0:255];
name: memories-read-writedescription: Test memories read-write supportshould_fail: 0tags: 7.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/memories/read-write.sv::11 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [7:0] mem [0:255];
name: copydescription: Test multidimensional word copyshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/copy.sv']incdirs: []top_module: rc: 0
name: basicdescription: Test multidimensional arraysshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv']incdirs: []top_module: rc: 0%Warning-LITENDIAN: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv:23: Little bit endian vector: MSB < LSB of bit range: 1:6%Warning-LITENDIAN: Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message.%Warning-LITENDIAN: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv:23: Little bit endian vector: MSB < LSB of bit range: 1:5
name: multi-declarationdescription: Test multidimensional arraysshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/multi.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/multi.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/multi.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/multi.sv::11 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] [31:0] arr_a [1:5] [1:10], arr_b [0:255];
name: copydescription: Test multidimensional word copyshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/copy.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/copy.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/copy.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/copy.sv::10 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [3:0] [7:0] arr_a [1:10];
name: basicdescription: Test multidimensional arraysshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/basic.sv::12 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [3:0] [7:0] arr [1:10];
name: subarraysdescription: Test multidimensional subarrays assignmentsshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int A[2][3][4], B[2][3][4];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv::13 error in parsing: (syntax error, unexpected '[', expecting voLTE or '=') A[0][2][0] = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv::20 error in parsing: (syntax error, unexpected '[', expecting ')') B[1][1][0], B[1][1][1], B[1][1][2], B[1][1][3]);ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: subarraysdescription: Test multidimensional subarrays assignmentsshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv:18: error: Cannot assign to array B['sd1]['sd1]. Did you forget a word index?1 error(s) during elaboration.
name: subarraysdescription: Test multidimensional subarrays assignmentsshould_fail: 0tags: 7.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/multidimensional/subarrays.sv']incdirs: []top_module: rc: 0module top; reg signed [767:0] A; reg signed [767:0] B; initial begin A[480+:32] = 5; A[448+:32] = 6; A[416+:32] = 7; A[384+:32] = 8; B[128+:128] = A[384+:128]; $display(":assert: ((%d == 5) and (%d == 6) and (%d == 7) and (%d == 8))", B[224+:32], B[192+:32], B[160+:32], B[128+:32]); endendmodule
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15:10: error: language feature not yet supported arr_a = '{1, 1, 1, 1, 1, 1, 1, 1}; ^~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:16:10: error: language feature not yet supported arr_b = '{0, 0, 0, 0, 0, 0, 0, 0}; ^~~~~~~~~~~~~~~~~~~~~~~~~
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: Illegal +: or -: select; type already selected, or bad dimension: type is UNPACKARRAYDTYPE%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: System task `$display' called with invalid/unsupported format specifier at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv:17.
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15: syntax error, unexpected $undefined
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr_a;
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_a [7:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')bit arr_b [7:0];
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/variable-slice.sv']incdirs: []top_module: rc: 0
name: operations-on-arrays-variable-slice-rwdescription: Test packed arrays operations support (Variable slice)should_fail: 0tags: 7.4.3 7.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:15: error: Cannot assign to array arr_a. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:16: error: Cannot assign to array arr_b. Did you forget a word index?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: error: Array cannot be indexed by a range./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/variable-slice.sv:22: error: Array cannot be indexed by a range.4 error(s) during elaboration.
name: basicdescription: Test dynamic arrays supportshould_fail: 0tags: 7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv
name: basicdescription: Test dynamic arrays supportshould_fail: 0tags: 7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv:9: syntax error, unexpected ']'
name: basicdescription: Test dynamic arrays supportshould_fail: 0tags: 7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr[];
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:9:14: error: dimension requires a constant rangebit [7:0] arr[]; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:12:11: error: language feature not yet supported arr = new [ 4 ]; ^~~~~~~~~
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 0
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:12: syntax error, unexpected '[', expecting TYPE-IDENTIFIER%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:9: syntax error, unexpected ']'
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr[];
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 0
name: dynamic-arrays-op-newdescription: Test dynamic arrays operator new supportshould_fail: 0tags: 7.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-new.sv:9:15: Parse error: unexpected token ']' (Sym_brack_r).
name: dynamic-arrays-op-sizedescription: Test dynamic arrays operator size supportshould_fail: 0tags: 7.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv:9:14: error: dimension requires a constant rangebit [7:0] arr[]; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv:12:11: error: language feature not yet supported arr = new [ 16 ]; ^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv:14:11: error: language feature not yet supported arr = new [ 8 ]; ^~~~~~~~~
name: dynamic-arrays-op-sizedescription: Test dynamic arrays operator size supportshould_fail: 0tags: 7.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-size.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr[];
name: dynamic-arrays-op-deletedescription: Test dynamic arrays operator delete supportshould_fail: 0tags: 7.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr[];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') arr.delete;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/dynamic/op-delete.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int A [3:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int B [0:3];
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv:18: error: Cannot assign to array B. Did you forget a word index?1 error(s) during elaboration.
name: array-unpacked-assignmentsdescription: Test unpacked arrays assignmentsshould_fail: 0tags: 7.6 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/assignments.sv']incdirs: []top_module: rc: 0module top; reg signed [127:0] A; reg signed [127:0] B; initial begin A[0+:32] = 0; A[32+:32] = 1; A[64+:32] = 2; A[96+:32] = 3; B = A; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2) and (%d == 3))", B[0+:32], B[32+:32], B[64+:32], B[96+:32]); endendmodule
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:9: syntax error, unexpected TOK_ID, expecting ',' or ')' or '['
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')task fun(int a [2:0]);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::12 error in parsing: (syntax error, unexpected vENDTASK)endtask;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') int b [2:0];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv::21 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#') fun(b);ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv:12: error: invalid module item.
name: unpacked-arrays-as-arguments-to-subroutinesdescription: Test support of arrays as arugments to subroutinesshould_fail: 0tags: 7.7 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/subroutines.sv']incdirs: []top_module: rc: 0module top; task fun; reg signed [95:0] a; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", a[0+:32], a[32+:32], a[64+:32]); endtask initial begin : sv2v_autoblock_0 reg signed [95:0] b; b[0+:32] = 0; b[32+:32] = 1; b[64+:32] = 2; $display(":assert: ((%d == 0) and (%d == 1) and (%d == 2))", b[0+:32], b[32+:32], b[64+:32]); fun(b); endendmodule
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:9: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-other-typesdescription: Test associative arrays supportshould_fail: 0tags: 7.8.5 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv:9: syntax error, unexpected '{', expecting '(' or '['
name: associative-arrays-wildcarddescription: Test associative arrays supportshould_fail: 0tags: 7.8.1 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [*];
name: associative-arrays-as-argumentsdescription: Test passing associative array as arugments supportshould_fail: 0tags: 7.9.10 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string arraya[int];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')task fun (string arrayb[int]);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::15 error in parsing: (syntax error, unexpected vENDTASK)endtaskPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::25 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#') fun(arraya);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::29 error in parsing: (syntax error, unexpected vEND)endERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: associative-arrays-literalsdescription: Test associative arrays literals supportshould_fail: 0tags: 7.9.11 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string words [int] = '{default: "hello"};
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')class C;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(') int x;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')int arr [ C ];
name: associative-arrays-integraldescription: Test associative arrays supportshould_fail: 0tags: 7.8.4 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ integer ];
name: associative-arrays-assignmentdescription: Test associative arrays assignment supportshould_fail: 0tags: 7.9.9 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string words [ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string w [ int ];
name: associative-arrays-stringdescription: Test associative arrays supportshould_fail: 0tags: 7.8.2 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ string ];
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-other-typesdescription: Test associative arrays supportshould_fail: 0tags: 7.8.5 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(')typedef struct {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv::11 error in parsing: (syntax error, unexpected '[', expecting '(') int I[*];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/other.sv::14 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ Unpkt ];
name: associative-arrays-as-argumentsdescription: Test passing associative array as arugments supportshould_fail: 0tags: 7.9.10 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv']incdirs: []top_module: rc: 9/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:9: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: error: Error in task/function port item after port name arrayb./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:13: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: error: Array ``arrayb'' has already been declared./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: error: Array ``arrayb'' has already been declared.
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: 3/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: error: Type names are not valid expressions here./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: internal error: I do not know how to elaborate this expression. /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: : Expression is: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: internal error: There is a problem evaluating indices for ``arr''.3 error(s) during elaboration.
name: associative-arrays-wildcarddescription: Test associative arrays supportshould_fail: 0tags: 7.8.1 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv:9: syntax error, unexpected [*, expecting ',' or ';'%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv
name: associative-arrays-wildcarddescription: Test associative arrays supportshould_fail: 0tags: 7.8.1 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv:9: syntax error, unexpected '*'
name: associative-arrays-wildcarddescription: Test associative arrays supportshould_fail: 0tags: 7.8.1 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/wildcard.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [*];
name: associative-arrays-stringdescription: Test associative arrays supportshould_fail: 0tags: 7.8.2 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/string.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ string ];
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:9: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:9: syntax error, unexpected ';', expecting '(' or '['
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')class C;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(') int x;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')int arr [ C ];
name: associative-arrays-classdescription: Test associative arrays supportshould_fail: 0tags: 7.8.3 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv']incdirs: []top_module: rc: 3/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: error: Type names are not valid expressions here./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: internal error: I do not know how to elaborate this expression. /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: : Expression is: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/class.sv:13: internal error: There is a problem evaluating indices for ``arr''.3 error(s) during elaboration.
name: associative-arrays-integraldescription: Test associative arrays supportshould_fail: 0tags: 7.8.4 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv:9: syntax error, unexpected TOK_INTEGER
name: associative-arrays-integraldescription: Test associative arrays supportshould_fail: 0tags: 7.8.4 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/integral.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ integer ];
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 0
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 0
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9:13: error: expected expressionstring map[ int ]; ^~~
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 0
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 0
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 0
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 0
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 0
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 0
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 0
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 0
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 0
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::18 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') map.delete;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::20 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string map[ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')byte ix;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: error: invalid module item.
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: error: invalid module item.
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: error: invalid module item.
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: error: invalid module item.
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: error: invalid module item.
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: error: invalid module item.
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: error: invalid module item.
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: error: invalid module item.
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: error: invalid module item.
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9:15: Parse error: unexpected token ']' (Sym_brack_r).
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9:15: Parse error: unexpected token ']' (Sym_brack_r).
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9:11: error: expected expressionint arr [ int ]; ^~~
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 0
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 0
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 0
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 0
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-access-nonexistentdescription: Test access to nonexistent associative array elementshould_fail: 0tags: 7.8.6 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/nonexistent.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: associative-arrays-allocating-elementsdescription: Test associative arrays elements allocationshould_fail: 0tags: 7.8.7 7.8 7.9.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/alloc.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr [ int ];
name: associative-arrays-numdescription: Test support of associative arrays methods (num)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/num.sv:9:15: Parse error: unexpected token ']' (Sym_brack_r).
name: associative-arrays-sizedescription: Test support of associative arrays methods (size)should_fail: 0tags: 7.9.1 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/size.sv:9:15: Parse error: unexpected token ']' (Sym_brack_r).
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 0
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::18 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') map.delete;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv::20 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9: error: invalid module item.
name: associative-arrays-deletedescription: Test support of associative arrays methods (delete)should_fail: 0tags: 7.9.2 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/delete.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 0
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9: error: invalid module item.
name: associative-arrays-existsdescription: Test support of associative arrays methods (exists)should_fail: 0tags: 7.9.3 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/exists.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 0
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9: error: invalid module item.
name: associative-arrays-firstdescription: Test support of associative arrays methods (first)should_fail: 0tags: 7.9.4 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/first.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 0
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9: error: invalid module item.
name: associative-arrays-lastdescription: Test support of associative arrays methods (last)should_fail: 0tags: 7.9.5 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/last.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 0
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9: error: invalid module item.
name: associative-arrays-nextdescription: Test support of associative arrays methods (next)should_fail: 0tags: 7.9.6 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/next.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9:11: error: expected expressionint map [ string ]; ^~~~~~
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 0
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int map [ string ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')string s;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9: error: invalid module item.
name: associative-arrays-prevdescription: Test support of associative arrays methods (prev)should_fail: 0tags: 7.9.7 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/prev.sv:9:11: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9:13: error: expected expressionstring map[ int ]; ^~~
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 0
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error, unexpected ']', expecting "'{"%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string map[ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')byte ix;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int rc;
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9: error: invalid module item.
name: associative-arrays-arg-traversaldescription: Test support of associative arrays methodsshould_fail: 0tags: 7.9.8 7.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/methods/traversal.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: associative-arrays-assignmentdescription: Test associative arrays assignment supportshould_fail: 0tags: 7.9.9 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv:9:16: error: expected expressionstring words [ int ]; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv:10:12: error: expected expressionstring w [ int ]; ^~~
name: associative-arrays-assignmentdescription: Test associative arrays assignment supportshould_fail: 0tags: 7.9.9 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string words [ int ];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/assignment.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string w [ int ];
name: associative-arrays-as-argumentsdescription: Test passing associative array as arugments supportshould_fail: 0tags: 7.9.10 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:9: syntax error, unexpected ';', expecting '('
name: associative-arrays-as-argumentsdescription: Test passing associative array as arugments supportshould_fail: 0tags: 7.9.10 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string arraya[int];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')task fun (string arrayb[int]);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::15 error in parsing: (syntax error, unexpected vENDTASK)endtaskPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::25 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#') fun(arraya);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv::29 error in parsing: (syntax error, unexpected vEND)endERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: associative-arrays-as-argumentsdescription: Test passing associative array as arugments supportshould_fail: 0tags: 7.9.10 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv']incdirs: []top_module: rc: 9/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:9: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: error: Error in task/function port item after port name arrayb./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:13: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: error: Array ``arrayb'' has already been declared./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: internal error: How can there be an unpacked range here?/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/arguments.sv:14: error: Array ``arrayb'' has already been declared.
name: associative-arrays-literalsdescription: Test associative arrays literals supportshould_fail: 0tags: 7.9.11 7.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/literals.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string words [int] = '{default: "hello"};
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -11
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv:9:6: error: dimension requires a constant rangeint q[$:2]; // 3 elements ^~~~~
name: basicdescription: Test queues supportshould_fail: 0tags: 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 0
name: basicdescription: Test queues supportshould_fail: 0tags: 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv:9: syntax error, unexpected ';', expecting '('
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find with ( item == "sad" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_first with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_last with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_index with ( item == "world" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_last_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_first_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr[] = { 0, 1, 3, 3 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') q = arr.find with ( item == item.index );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:2]; // 3 elements
name: basicdescription: Test queues supportshould_fail: 0tags: 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/basic.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: error: malformed statement
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: error: malformed statement
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: error: malformed statement
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: error: malformed statement
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: error: malformed statement
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: error: malformed statement
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: error: malformed statement
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd10, 'sd3, 'sd20, 'sd20, 'sd10}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: error: malformed statement
name: slicedescription: Test queues slice supportshould_fail: 0tags: 7.10.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:5];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int r[$];
name: max-sizedescription: Test queues size supportshould_fail: 0tags: 7.10.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:5];
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:9: syntax error, unexpected ';', expecting '('
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv:9: syntax error, unexpected ';', expecting '('
name: slicedescription: Test queues slice supportshould_fail: 0tags: 7.10.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:5];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/slice.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int r[$];
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::19 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') q.delete;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::21 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: sizedescription: Test queues size supportshould_fail: 0tags: 7.10.2.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: max-sizedescription: Test queues size supportshould_fail: 0tags: 7.10.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/max-size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:5];
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:12: error: Enable of unknown task ``q.insert''.1 error(s) during elaboration.
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: 0
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:16: error: Unable to bind wire/reg/memory `q.pop_back' in `top'1 error(s) during elaboration.
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:16: error: Unable to bind wire/reg/memory `q.pop_front' in `top'1 error(s) during elaboration.
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 0
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:2]; // 3 elements
name: sizedescription: Test queues size supportshould_fail: 0tags: 7.10.2.1 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 0
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:9: syntax error, unexpected ';', expecting '('
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:12: error: Enable of unknown task ``q.insert''.1 error(s) during elaboration.
name: insertdescription: Test queues insert function supportshould_fail: 0tags: 7.10.2.2 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 0
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv:9: syntax error, unexpected ';', expecting '('
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::19 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') q.delete;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv::21 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 0
name: deletedescription: Test queues delete function supportshould_fail: 0tags: 7.10.2.3 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 0
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:9: syntax error, unexpected ';', expecting '('
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:16: error: Unable to bind wire/reg/memory `q.pop_front' in `top'1 error(s) during elaboration.
name: pop_frontdescription: Test queues pop_front function supportshould_fail: 0tags: 7.10.2.4 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 0
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:9: syntax error, unexpected ';', expecting '('
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:16: error: Unable to bind wire/reg/memory `q.pop_back' in `top'1 error(s) during elaboration.
name: pop_backdescription: Test queues pop_back function supportshould_fail: 0tags: 7.10.2.5 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 0
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv:9: syntax error, unexpected ';', expecting '('
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 0
name: push_frontdescription: Test queues push_front function supportshould_fail: 0tags: 7.10.2.6 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv:9:6: error: dimension requires a constant rangeint q[$:2]; // 3 elements ^~~~~
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv:9: syntax error, unexpected ';', expecting '('
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:2]; // 3 elements
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: push_backdescription: Test queues push_back function supportshould_fail: 0tags: 7.10.2.7 7.10.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:9:6: error: dimension requires a constant rangeint q[$]; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:28:6: error: language feature not yet supported q = {}; ^~
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 0
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:9: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: ref%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:26: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:28: syntax error, unexpected '}', expecting TYPE-IDENTIFIER%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:29: Unsupported: Ignoring delay on this delayed statement.%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:9: syntax error, unexpected ';', expecting '('
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::11 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',')task automatic fun(ref int e);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::13 error in parsing: (syntax error, unexpected vDELAY_ID) #100PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::16 error in parsing: (syntax error, unexpected vENDTASK)endtaskPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::22 error in parsing: (syntax error, unexpected '(', expecting vSYMBOL_ID or '#') fun(q[1]);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv::31 error in parsing: (syntax error, unexpected vEND)endERROR (9)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:11: sorry: Reference ports not supported yet./home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:19: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3}1 error(s) during elaboration.
name: queues-elements-persistencedescription: Test status of persistence of references to elements of queueshould_fail: 0tags: 7.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/persistence.sv:9:7: Parse error: unexpected token '$' (Sym_dollar).
name: insertdescription: Update queue by assignment (insert)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv::13 error in parsing: (syntax error, unexpected ']') q = { q[0:1], 10, q[2:$] }; // q.insert(2, 10)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/insert_assign.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: push_back_assigndescription: Update queue by assignment (push_back)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: pop_backdescription: Update queue by assignment (pop_back)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back_assing.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back_assing.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back_assing.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back_assing.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_back_assing.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;
name: pop_frontdescription: Update queue by assignment (pop_front)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv::17 error in parsing: (syntax error, unexpected ']') q = q[1:$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/pop_front_assign.sv::21 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: deletedescription: Update queue by assignment (delete)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int r;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::17 error in parsing: (syntax error, unexpected ']') q = q[1:$]; // q.delete(0)PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::19 error in parsing: (syntax error, unexpected '=', expecting vSYMBOL_ID or '#') q = {}; // q.deletePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/delete_assign.sv::21 error in parsing: (syntax error, unexpected vEND)endERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: push_front_assigndescription: Update queue by assignment (push_front)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];
name: push_back_assigndescription: Update queue by assignment (push_back)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv']incdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv:12: internal error: I don't know how to elaborate(ivl_type_t) this expression: {q, 'sd4}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv:13: internal error: I don't know how to elaborate(ivl_type_t) this expression: {q, 'sd3}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_back_assign.sv:14: internal error: I don't know how to elaborate(ivl_type_t) this expression: {q, 'sd2}
name: push_front_assigndescription: Update queue by assignment (push_front)should_fail: 0tags: 7.10.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv']incdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv:12: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd2, q}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv:13: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd3, q}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/push_front_assign.sv:14: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd4, q}
name: bounded-queuesdescription: Test bounded queues supportshould_fail: 0tags: 7.10.5 7.10 7.10.2.7 7.10.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/queues/bounded.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$:2]; // 3 elements
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv:12:33: error: use of undeclared identifier '$unpacked_dimensions' $display(":assert: (%d == 0)", $unpacked_dimensions(arr)); ^~~~~~~~~~~~~~~~~~~~
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv:12:33: error: use of undeclared identifier '$dimensions' $display(":assert: (%d == 1)", $dimensions(arr)); ^~~~~~~~~~~
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$high' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv:12.
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$low' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv:12.
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$increment' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv:12.
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$size' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv:12.
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$unpacked_dimensions' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv:12.
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$right' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv:12.
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$dimensions' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv:12.
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Can't resolve function name `\$left' at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv:12.
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [7:0] arr;
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0
name: arrays-packed-quering-functions-highdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/high.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 7)", 7); endendmodule
name: arrays-packed-quering-functions-lowdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/low.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 0)", 0); endendmodule
name: arrays-packed-quering-functions-incrementdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/increment.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 1)", 1); endendmodule
name: arrays-packed-quering-functions-sizedescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/size.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 8)", 8); endendmodule
name: arrays-packed-quering-functions-unpacked-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/unpacked-dimensions.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 0)", 0); endendmodule
name: arrays-packed-quering-functions-rightdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/right.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 0)", 0); endendmodule
name: arrays-packed-quering-functions-dimensionsdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/dimensions.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 1)", 1); endendmodule
name: arrays-packed-quering-functions-leftdescription: Test quering functions support on packed arraysshould_fail: 0tags: 7.11 7.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/packed/querying-functions/left.sv']incdirs: []top_module: rc: 0module top; wire [7:0] arr; initial begin $display(":assert: (%d == 7)", 7); endendmodule
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error, unexpected unique%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9: syntax error, unexpected ']'
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9: syntax error, unexpected ']'
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find with ( item == "sad" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_first with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_last with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_index with ( item == "world" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_last_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_first_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: error: malformed statement
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: error: malformed statement
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: error: malformed statement
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: error: malformed statement
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: error: malformed statement
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: error: malformed statement
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: error: malformed statement
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd10, 'sd3, 'sd20, 'sd20, 'sd10}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 20, 2, 11, 5 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -11
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error, unexpected unique%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9: syntax error, unexpected ']'
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9: syntax error, unexpected ']'
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']'
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']'
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find with ( item == "sad" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_first with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 20, 2, 11, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')string qs[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qs = s.find_last with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_index with ( item == "world" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_last_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "hello", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') qi = s.find_first_index with ( item == "hello" );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr[] = { 0, 1, 3, 3 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') q = arr.find with ( item == item.index );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:13: error: malformed statement
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:13: error: malformed statement
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd20, 'sd2, 'sd11, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:13: error: malformed statement
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:13: error: malformed statement
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: error: malformed statement
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:13: error: malformed statement
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:13: error: malformed statement
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd10, 'sd3, 'sd20, 'sd20, 'sd10}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: error: malformed statement
name: array-locator-methods-finddescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-maxdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/max.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-firstdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-mindescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/min.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-lastdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-find-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-find-last-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-last-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-find-first-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/find-first-index.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9:9: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:6: error: dimension requires a constant rangeint s[] = { 10, 10, 3, 20, 20, 10 }; ^~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10:7: error: dimension requires a constant rangeint qi[$]; ^~~
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9:7: error: dimension requires a constant rangeint ia[] = { 4, 5, 3, 1 }; ^~
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9:9: error: dimension requires a constant rangestring s[] = { "hello", "sad", "world" }; ^~
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9:7: error: dimension requires a constant rangeint ia[] = { 1, 2, 3, 4, 5 }; ^~
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9:7: error: dimension requires a constant rangeint ia[] = { 4, 5, 3, 1 }; ^~
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 0
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 0
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 0
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 0
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 0
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error, unexpected unique%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: Exiting due to 2 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9: syntax error, unexpected ']'
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: syntax error, unexpected ']'
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: syntax error, unexpected ']'
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: syntax error, unexpected ']'
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: syntax error, unexpected ']'
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: syntax error, unexpected ']'
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int s[] = { 10, 10, 3, 20, 20, 10 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int qi[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::15 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') qi.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv::18 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 4, 5, 3, 1 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.sort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')string s[] = { "hello", "sad", "world" };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') s.reverse;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 1, 2, 3, 4, 5 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.shuffle;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int ia[] = { 4, 5, 3, 1 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::14 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') ia.rsort;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv::17 error in parsing: (syntax error, unexpected vEND)endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:13: error: malformed statement
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd10, 'sd10, 'sd3, 'sd20, 'sd20, 'sd10}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd4, 'sd5, 'sd3, 'sd1}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {"hello", "sad", "world"}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4, 'sd5}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd4, 'sd5, 'sd3, 'sd1}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: array-locator-methods-uniquedescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: array-locator-methods-unique-indexdescription: Test support of array locator methodsshould_fail: 0tags: 7.12.1 7.12 7.10 7.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/associative/locator-methods/unique-index.sv:9:7: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-sortdescription: Test support of sort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/sort.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-reversedescription: Test support of reverse method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/reverse.sv:9:1: Parse error: unexpected token 'string' (KW_string).
name: ordering-methods-shuffledescription: Test support of shuffle method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/shuffle.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: ordering-methods-rsortdescription: Test support of rsort method on unpacked arraysshould_fail: 0tags: 7.12.2 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/ordering-methods/rsort.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9:7: error: dimension requires a constant rangebyte b[] = { 1, 2, 3, 4 }; ^~
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9:7: error: dimension requires a constant rangebyte b[] = { 1, 2, 3, 4 }; ^~
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9:7: error: dimension requires a constant rangebyte b[] = { 1, 2, 3, 4 }; ^~
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9:7: error: dimension requires a constant rangebyte b[] = { 1, 2, 3, 4 }; ^~
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9:7: error: dimension requires a constant rangebyte b[] = { 1, 3, 5, 7 }; ^~
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 0
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9: syntax error, unexpected ']'
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 2, 3, 4 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')byte b[] = { 1, 3, 5, 7 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int y;
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:15: error: malformed statement
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:15: error: malformed statement
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: internal error: I don't know how to elaborate(ivl_type_t) this expression: {'sd1, 'sd2, 'sd3, 'sd4}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9: assert: elaborate.cc:2321: failed assertion !is_constant_Aborted (core dumped)
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:15: error: malformed statement
name: unpacked-array-reduction-method-ordescription: Test support of unpacked arrays reduction method orshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/or.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-xordescription: Test support of unpacked arrays reduction method xorshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/xor.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-productdescription: Test support of unpacked arrays reduction method productshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/product.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-sumdescription: Test support of unpacked arrays reduction method sumshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/sum.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-reduction-method-anddescription: Test support of unpacked arrays reduction method andshould_fail: 0tags: 7.12.3 7.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/reduction-methods/and.sv:9:8: Parse error: unexpected token ']' (Sym_brack_r).
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -11
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 0
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:10: syntax error, unexpected $undefined, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: with%Error: Exiting due to 3 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9: syntax error, unexpected ']'
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(')int arr[] = { 0, 1, 3, 3 };PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::10 error in parsing: (syntax error, unexpected '[', expecting '(')int q[$];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') q = arr.find with ( item == item.index );PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv::16 error in parsing: (syntax error, unexpected vEND)endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:13: error: malformed statement
name: unpacked-array-iterator-index-queryingdescription: Test support of unpacked arrays index querying methodshould_fail: 0tags: 7.12.4 7.4.2 7.10 7.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-7/arrays/unpacked/index.sv:9:9: Parse error: unexpected token ']' (Sym_brack_r).
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:7:1: error: language feature not yet supportedclass Foo;^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9:9: error: expected identifierfunction new (integer size); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9:10: error: expected statementfunction new (integer size); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9:27: error: expected declaratorfunction new (integer size); ^
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:7:1: error: language feature not yet supportedclass event_calendar;^~~~~~~~~~~~~~~~~~~~~
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:7:1: error: language feature not yet supportedclass pp_as_class_item;^~~~~~~~~~~~~~~~~~~~~~~
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_29description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7:1: error: language feature not yet supportedclass Foo extends Base implements Pkg::Bar, Baz; endclass^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_12description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7:1: error: language feature not yet supportedclass Foo #(int N=1, int P=2) extends Bar #(x,y,z);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_16description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7:1: error: language feature not yet supportedclass Foo #(IFType=virtual x_if);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_61description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_11description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7:1: error: language feature not yet supportedclass Foo #(int N, int P);^~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_60description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_55description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:7:1: error: language feature not yet supportedclass Driver;^~~~~~~~~~~~~
name: class_test_41description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:7:1: error: language feature not yet supportedclass macros_as_class_item;^~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:8:2: error: unknown macro or compiler directive '`uvm_object_utils' `uvm_object_utils(stress_seq) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:9:2: error: unknown macro or compiler directive '`uvm_object_registry' `uvm_object_registry(myclass, "class_name") ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:10:2: error: unknown macro or compiler directive '`uvm_sweets' `uvm_sweets(dessert) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:11:2: error: unknown macro or compiler directive '`non_uvm_macro' `non_uvm_macro(apple, `banana, "cherry") ^
name: class_test_68description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_56description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:7:1: error: language feature not yet supportedclass Driver;^~~~~~~~~~~~~
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7:1: error: language feature not yet supportedclass pp_class;^~~~~~~~~~~~~~~
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7:1: error: language feature not yet supportedvirtual class Foo; endclass^~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7:1: error: language feature not yet supportedclass macros_as_class_item;^~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:8:2: error: unknown macro or compiler directive '`moobar' `moobar(,) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:9:2: error: unknown macro or compiler directive '`zoobar' `zoobar( , ) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:10:2: error: unknown macro or compiler directive '`zootar' `zootar(12,) ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:11:2: error: unknown macro or compiler directive '`zoojar' `zoojar(,34) ^
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv:7:15: error: forward typedef 'myclass_fwd' does not resolve to a data typetypedef class myclass_fwd; ^
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7:1: error: language feature not yet supportedclass Foo #(T=int);^~~~~~~~~~~~~~~~~~~
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7:1: error: language feature not yet supportedclass Foo extends Package::Bar; endclass^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7:1: error: language feature not yet supportedclass zzxx;^~~~~~~~~~~
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7:1: error: language feature not yet supportedclass Foo #(type IFType=virtual x_if);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7:1: error: language feature not yet supportedclass foo;^~~~~~~~~~
name: class_test_40description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:7:1: error: language feature not yet supportedclass macros_as_class_item;^~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:8:2: error: unknown macro or compiler directive '`uvm_object_registry' `uvm_object_registry(myclass, "class_name") ^
name: class_test_51description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:7:1: error: language feature not yet supportedclass how_wide;^~~~~~~~~~~~~~~
name: class_member_test_33description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_44description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:8:16: error: expected identifierextern function new; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:8:17: error: expected memberextern function new; ^~~
name: class_member_test_54description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:7:1: error: language feature not yet supportedclass myclass extends uvm_object;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_34description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_31description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_12description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv:7:1: error: language feature not yet supportedclass semaphore;^~~~~~~~~~~~~~~~
name: class_member_test_36description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_50description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:8:1: error: unexpected qualifiers on class membervirtual hinterface.some_mod_port winterface;^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:8:9: error: expected membervirtual hinterface.some_mod_port winterface; ^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:10:1: error: unexpected qualifiers on class membervirtual disinterface#(.N(N)).some_mod_port blinterface;^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:10:9: error: expected membervirtual disinterface#(.N(N)).some_mod_port blinterface; ^~~~~~~~~~~~
name: class_member_test_53description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:7:1: error: language feature not yet supportedclass myclass extends uvm_object;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_47description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:7:1: error: language feature not yet supportedclass fun_with_typedef_members;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_9description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_40description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:8:9: error: expected identifierfunction new (); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:8:10: error: expected statementfunction new (); ^~~
name: class_member_test_28description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_56description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:7:1: error: language feature not yet supportedclass myclass extends uvm_object;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_45description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:8:16: error: expected identifierextern function new(); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:8:17: error: expected memberextern function new(); ^~~
name: class_member_test_58description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:7:1: error: language feature not yet supportedclass myclass extends uvm_object;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:12: error: expected expression solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:13: error: expected ',' solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:15: error: expected expression solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:16: error: expected ',' solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:27: error: expected expression solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:28: error: expected ',' solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:30: error: expected expression solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11:31: error: expected ',' solve x.z, f, g before q, r, y.x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:15: error: expected expression solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:16: error: expected ',' solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:21: error: expected expression solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:22: error: expected ',' solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:33: error: expected expression solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:34: error: expected ',' solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:39: error: expected expression solve x.z[2], f[1], g before q, r[4], y[3].x; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12:40: error: expected ',' solve x.z[2], f[1], g before q, r[4], y[3].x; ^
name: class_member_test_2description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_25description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_13description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:7:1: error: language feature not yet supportedclass protected_stuff;^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9:34: error: unknown macro or compiler directive '`SSS' protected const int countess = `SSS; ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9:38: error: expected expression protected const int countess = `SSS; ^
name: class_member_test_0description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_22description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8:32: error: expected identifierextern function sometype #(N+1)[N:0]subr(ducktype #(3) x); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8:37: error: expected ';'extern function sometype #(N+1)[N:0]subr(ducktype #(3) x); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8:37: error: expected memberextern function sometype #(N+1)[N:0]subr(ducktype #(3) x); ^~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8:57: error: expected declaratorextern function sometype #(N+1)[N:0]subr(ducktype #(3) x); ^
name: class_member_test_1description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv:7:1: error: language feature not yet supportedclass c;^~~~~~~~
name: class_member_test_20description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_27description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_57description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:7:1: error: language feature not yet supportedclass foo_class extends bar;^~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_4description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_23description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_21description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_49description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_26description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_51description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_24description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_46description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:16: error: expected identifierextern function new(string name, int count); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:17: error: expected memberextern function new(string name, int count); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:33: error: expected identifierextern function new(string name, int count); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:34: error: expected declaratorextern function new(string name, int count); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:37: error: expected ','extern function new(string name, int count); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8:43: error: expected declaratorextern function new(string name, int count); ^
name: class_member_test_32description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_14description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_48description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_19description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_3description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_8description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_15description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_35description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_55description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:7:1: error: language feature not yet supportedclass myclass extends uvm_object;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: class_member_test_52description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_38description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_10description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:7:1: error: language feature not yet supportedclass outerclass;^~~~~~~~~~~~~~~~~
name: class_member_test_42description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:9: error: expected identifierfunction new (string name, virtual time_if vif); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:10: error: expected statementfunction new (string name, virtual time_if vif); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:27: error: expected identifierfunction new (string name, virtual time_if vif); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:28: error: expected declaratorfunction new (string name, virtual time_if vif); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:35: error: expected ','function new (string name, virtual time_if vif); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:43: error: expected ','function new (string name, virtual time_if vif); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8:47: error: expected declaratorfunction new (string name, virtual time_if vif); ^
name: class_member_test_7description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_29description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_11description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_6description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_37description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_17description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_18description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_16description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_43description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8:9: error: expected identifierfunction new (foo::bar name, ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8:10: error: expected statementfunction new (foo::bar name, ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8:29: error: expected identifierfunction new (foo::bar name, ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:9:5: error: expected declarator virtual interface time_if vif, ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:9:22: error: expected ',' virtual interface time_if vif, ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:9:30: error: expected ',' virtual interface time_if vif, ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:8: error: expected declarator baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:10: error: expected ',' baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:13: error: expected declarator baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:16: error: expected ',' baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:19: error: expected ',' baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:24: error: expected identifier baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:25: error: expected declarator baz#(M,N)::foo bar, bit [K:0] b); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:30: error: expected ',' baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:31: error: expected declarator baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:34: error: expected ',' baz#(M,N)::foo bar, bit [K:0] b); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10:36: error: expected declarator baz#(M,N)::foo bar, bit [K:0] b); ^
name: class_member_test_41description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:7:1: error: language feature not yet supportedclass constructible;^~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:8:9: error: expected identifierfunction new (); ^../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:8:10: error: expected statementfunction new (); ^~~
name: class_member_test_30description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: class_member_test_5description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:7:1: error: language feature not yet supportedclass myclass;^~~~~~~~~~~~~~
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7:1: error: language feature not yet supportedinterface class base_ic extends basebase;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:7:1: error: language feature not yet supportedinterface class base_ic #(int N = 8, type T = string);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7:1: error: language feature not yet supportedinterface class base_ic extends base1, base2, base3;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7:1: error: language feature not yet supportedinterface class base_ic #(int N = 8) extends pkg1::base1, base2#(N);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:9: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv
name: class_test_29description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv
name: class_test_12description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: syntax error, unexpected ')', expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv
name: class_test_16description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv
name: class_test_61description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv
name: class_test_11description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:7: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv
name: class_test_60description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv
name: class_test_55description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv
name: class_test_41description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:8: Define or directive not defined: `uvm_object_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:9: Define or directive not defined: `uvm_object_registry%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:10: Define or directive not defined: `uvm_sweets%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:11: Define or directive not defined: `non_uvm_macro%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:11: Define or directive not defined: `banana%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv
name: class_test_68description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv
name: class_test_56description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv
name: class_test_20description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:8: Define or directive not defined: `moobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:9: Define or directive not defined: `zoobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:10: Define or directive not defined: `zootar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:11: Define or directive not defined: `zoojar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax error, unexpected '#', expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv
name: class_test_0description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv
name: class_test_23description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv
name: class_test_64description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv
name: class_test_24description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv
name: class_test_43description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:8: Define or directive not defined: `uvm_object_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:10: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:12: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv
name: class_test_10description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:7: syntax error, unexpected ')', expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv
name: class_test_58description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:8: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv
name: class_test_42description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:8: Define or directive not defined: `uvm_object_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:9: Define or directive not defined: `uvm_object_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:10: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv
name: class_test_25description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv
name: class_test_53description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:11: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:11: Perhaps 'mypkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:12: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv
name: class_test_3description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv
name: class_test_28description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv
name: class_test_6description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv
name: class_test_49description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:10: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:10: Perhaps 'glb' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv
name: class_test_50description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv
name: class_test_66description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv
name: class_test_52description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv
name: class_test_18description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv
name: class_test_13description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: syntax error, unexpected type, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv
name: class_test_44description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:8: Define or directive not defined: `uvm_field_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:10: Define or directive not defined: `uvm_field_real%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:12: Define or directive not defined: `uvm_field_object%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:13: Define or directive not defined: `uvm_field_event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:14: Define or directive not defined: `uvm_field_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:15: Define or directive not defined: `uvm_field_array_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:16: Define or directive not defined: `uvm_field_sarray_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:17: Define or directive not defined: `uvm_field_aa_int_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:18: Define or directive not defined: `uvm_field_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv
name: class_test_8description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv
name: class_test_21description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: Define or directive not defined: `moobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:9: Define or directive not defined: `zoobar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:10: Define or directive not defined: `zootar%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: Perhaps 'dbg_pkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv
name: class_test_22description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv
name: class_test_19description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv
name: class_test_47description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:8: Define or directive not defined: `uvm_new_func%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:9: Define or directive not defined: `uvm_new_func2%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:10: Define or directive not defined: `uvm_new_func3%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv
name: class_test_26description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv
name: class_test_2description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: Perhaps 'dbg_pkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv
name: class_test_9description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv
name: class_test_15description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv
name: class_test_46description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:8: Define or directive not defined: `uvm_component_utils%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:9: Define or directive not defined: `uvm_component_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:10: Define or directive not defined: `uvm_field_object%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:11: Define or directive not defined: `uvm_field_event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:12: Define or directive not defined: `uvm_field_string%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:13: Define or directive not defined: `uvm_component_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 9 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv
name: class_test_37description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv
name: class_test_45description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:8: Define or directive not defined: `uvm_object_param_utils_begin%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:9: Define or directive not defined: `uvm_field_int%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:10: Define or directive not defined: `uvm_field_real%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:11: Define or directive not defined: `uvm_field_enum%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:12: Define or directive not defined: `uvm_object_utils_end%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv
name: class_test_1description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv
name: class_test_5description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv
name: class_test_57description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv
name: class_test_35description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv:10: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv
name: class_test_67description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv
name: class_test_27description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv
name: class_test_40description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:8: Define or directive not defined: `uvm_object_registry%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv
name: class_test_51description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv
name: class_member_test_33description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv:10: syntax error, unexpected ',', expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv
name: class_member_test_44description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv
name: class_member_test_54description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv
name: class_member_test_34description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv
name: class_member_test_31description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:9: syntax error, unexpected ','%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:9: syntax error, unexpected ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:10: syntax error, unexpected ')', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv
name: class_member_test_12description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv
name: class_member_test_36description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:8: syntax error, unexpected IDENTIFIER, expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv
name: class_member_test_50description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:9: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv
name: class_member_test_53description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv
name: class_member_test_47description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:10: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:12: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:13: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv
name: class_member_test_9description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:8: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv
name: class_member_test_40description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv
name: class_member_test_28description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:9: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:9: syntax error, unexpected ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:10: syntax error, unexpected ')', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv
name: class_member_test_56description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:9: Unsupported: SystemVerilog 2012 reserved word not implemented: soft%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: dist%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv
name: class_member_test_45description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv
name: class_member_test_58description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: solve%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: before%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: solve%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: before%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: solve%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: before%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: solve%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: before%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 13 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv
name: class_member_test_2description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv
name: class_member_test_25description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:10: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv
name: class_member_test_13description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: Define or directive not defined: `SSS%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:12: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv
name: class_member_test_0description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv
name: class_member_test_22description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:8: syntax error, unexpected '#', expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv
name: class_member_test_1description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv:8: syntax error, unexpected '.', expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv
name: class_member_test_20description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:8: syntax error, unexpected '#', expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv
name: class_member_test_27description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv
name: class_member_test_57description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: dist%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv
name: class_member_test_4description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv
name: class_member_test_23description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: Perhaps 'mypkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv
name: class_member_test_21description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:8: syntax error, unexpected '#', expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv
name: class_member_test_49description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:9: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv
name: class_member_test_26description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:9: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv
name: class_member_test_51description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv
name: class_member_test_24description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: Perhaps 'mypkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv
name: class_member_test_46description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8: syntax error, unexpected int, expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv
name: class_member_test_32description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:9: syntax error, unexpected var, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:9: syntax error, unexpected ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:10: syntax error, unexpected ')', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv
name: class_member_test_14description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv
name: class_member_test_48description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:9: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv
name: class_member_test_19description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv
name: class_member_test_3description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv
name: class_member_test_8description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv
name: class_member_test_15description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:10: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv
name: class_member_test_35description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:8: syntax error, unexpected IDENTIFIER, expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv
name: class_member_test_39description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv
name: class_member_test_55description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:8: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: constraint%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:9: Unsupported: SystemVerilog 2012 reserved word not implemented: soft%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv
name: class_member_test_52description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:8: syntax error, unexpected ::, expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:8: Perhaps 'apkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 8 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv
name: class_member_test_38description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:8: syntax error, unexpected '.', expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv
name: class_member_test_10description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv
name: class_member_test_42description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:8: syntax error, unexpected IDENTIFIER, expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv
name: class_member_test_7description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv
name: class_member_test_29description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:9: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:9: syntax error, unexpected ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv
name: class_member_test_11description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv
name: class_member_test_6description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv
name: class_member_test_37description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv
name: class_member_test_17description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:8: syntax error, unexpected ::, expecting '(' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:8: Perhaps 'yourpkg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv
name: class_member_test_18description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv
name: class_member_test_16description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: extern%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv:10: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv
name: class_member_test_43description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: syntax error, unexpected ')', expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv
name: class_member_test_41description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv
name: class_member_test_30description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:9: syntax error, unexpected ','%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:9: syntax error, unexpected ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:10: syntax error, unexpected ')', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv
name: class_member_test_5description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:7: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:9: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:8: syntax error, unexpected ':'%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:9: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:9: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:10: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:11: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:8: syntax error, unexpected '[', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:11: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:10: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:10: Perhaps 'bhg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:8: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:8: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:9: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class event_calendar;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_29description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_29.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Base implements Pkg::Bar, Baz; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_12description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_12.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N=1, int P=2) extends Bar #(x,y,z);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_16description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_16.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(IFType=virtual x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_61description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_61.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_11description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N, int P);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_60description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_60.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_55description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_55.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Driver;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_41description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_41.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_68description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_68.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_56description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_56.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Driver;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_20description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_20.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(.v1(x),.v2(y)); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_69description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_69.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_63description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_63.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_4description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_39description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_39.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_31description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_31.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)typedef class myclass_fwd;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_14description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_14.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(T=int);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_7description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_17description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_17.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type IFType=virtual x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_36description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_36.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class foo;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_0description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class semicolon_classy; ; ;;; ; ; ;endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_23description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_23.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_64description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_64.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_24description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_24.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar, Blah, Baz; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_43description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_43.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_10description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N, P);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_58description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_58.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class fields_with_modifiers;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_42description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_42.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_25description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_25.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Package::Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_53description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_53.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class param_types_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_3description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class automatic Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_28description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_28.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Base implements Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_6description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Bar; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_49description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_49.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class params_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_50description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_50.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class params_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_66description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_66.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_52description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_52.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class how_wide #(type DT=int) extends uvm_sequence_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_18description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_18.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type IFType=virtual interface x_if);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_13description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_13.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int W=8, type Int=int) extends Bar #(x,y,z);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_44description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_44.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_8description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_21description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_21.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxy;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_22description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_22.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(.v1(x),.v2(y)); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_19description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_19.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo extends Package::Bar #(x,y,z); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_47description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_47.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_id_as_call;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_26description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_26.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Bar#(N); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_2description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class static Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzyyy;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_9description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(int N);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_15description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_15.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo #(type KeyType=int, Int=int);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_46description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_46.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_37description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_37.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class foo extends bar;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_45description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_45.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_1description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_5description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)virtual class automatic Foo; endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_57description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_57.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class fields_with_modifiers;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_35description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_35.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class zzxx;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_67description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_67.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class pp_class;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_27description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_27.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class Foo implements Package::Bar#(1, 2); endclassERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_40description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_40.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class macros_as_class_item;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_51description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_51.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class how_wide;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_33description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_33.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_44description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_44.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_54description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_54.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass extends uvm_object;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_34description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_34.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_31description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_31.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_12description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_12.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class semaphore;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_36description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_36.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_50description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_50.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_53description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_53.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass extends uvm_object;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_47description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_47.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class fun_with_typedef_members;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_9description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_40description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_40.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_28description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_28.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_56description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_56.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass extends uvm_object;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_45description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_45.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_58description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_58.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass extends uvm_object;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_2description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_25description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_13description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class protected_stuff;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_0description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_22description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_22.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_1description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class c;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_20description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_27description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_57description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_57.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class foo_class extends bar;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_4description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_23description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_21description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_21.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_49description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_49.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_26description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_26.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_51description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_24description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_46description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_32description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_32.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_14description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_14.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_48description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_48.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_19description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_19.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_3description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_8description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_15description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_35description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_39description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_55description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_55.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass extends uvm_object;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_52description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_52.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_38description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_38.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_10description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class outerclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_42description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_42.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_7description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_29description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_29.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_11description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_6description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_37description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_17description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_17.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_18description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_18.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_16description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_16.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_43description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_41description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class constructible;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_30description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_30.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_member_test_5description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)class myclass;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic extends basebase;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic #(int N = 8, type T = string);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic extends base1, base2, base3;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic #(int N = 8) extends pkg1::base1, base2#(N);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: class_test_30description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_30.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_54description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:8: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:9: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_54.sv:10: error: invalid class item.
name: class_test_48description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_48.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_65description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_65.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_62description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_62.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_32description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: error: Error in task/function port item after port name analysis_port./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_32.sv:8: syntax errorI give up.
name: class_test_59description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_59.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_test_38description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: warning: macro moobar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:9: warning: macro zoobar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:10: warning: macro zootar undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_38.sv:8: syntax errorI give up.
name: class_test_33description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: error: Error in task/function port item after port name dbg_pkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_33.sv:8: syntax errorI give up.
name: class_test_34description: Testshould_fail: 0tags: 6.15 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: error: Error in task/function port item after port name dbg_pkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/generic/class/class_test_34.sv:8: syntax errorI give up.
name: class_member_test_2description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:8: error: Error in task/function port item after port name arg_type./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_2.sv:8: syntax errorI give up.
name: class_member_test_25description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_25.sv:8: sorry: External methods are not yet supported.
name: class_member_test_13description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: warning: macro SSS undefined (and assumed null) at this point./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:9: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:10: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:11: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_13.sv:12: error: invalid class item.
name: class_member_test_0description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_0.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_member_test_20description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:8: error: Error in task/function port item after port name ducktype./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_20.sv:8: syntax errorI give up.
name: class_member_test_27description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:8: error: Error in task/function port item after port name uvm_phase./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_27.sv:8: syntax errorI give up.
name: class_member_test_4description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: error: Error in task/function port item after port name arg_type./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_4.sv:8: syntax errorI give up.
name: class_member_test_23description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: error: Error in task/function port item after port name mypkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_23.sv:8: syntax errorI give up.
name: class_member_test_51description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_51.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_member_test_24description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: error: Error in task/function port item after port name mypkg./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_24.sv:8: syntax errorI give up.
name: class_member_test_46description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_46.sv:8: sorry: External constructors are not yet supported.
name: class_member_test_15description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_15.sv:8: sorry: External methods are not yet supported.
name: class_member_test_35description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:8: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_35.sv:9: syntax errorI give up.
name: class_member_test_39description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_39.sv:1: error: I give up on this class constructor declaration.
name: class_member_test_11description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_11.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: class_member_test_6description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: error: Error in task/function port item after port name arg_type./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_6.sv:8: syntax errorI give up.
name: class_member_test_37description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:9: error: invalid class item./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_37.sv:10: syntax errorI give up.
name: class_member_test_43description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv']incdirs: []top_module: rc: 9/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8: error: Error in task/function port item after port name foo./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: error: Error in task/function port item after port name baz./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:9: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: error: Syntax error in task/function port declaration./home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_43.sv:10: error: Syntax error in task/function port declaration.
name: class_member_test_41description: Testshould_fail: 0tags: 8.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/member/class_member_test_41.sv']incdirs: []top_module: rc: 1No top level modules, and no -s option.
name: instantiationdescription: simple class instantiation testshould_fail: 0tags: 8.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:12:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~
name: instantiationdescription: simple class instantiation testshould_fail: 0tags: 8.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: null%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:15: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv
name: instantiationdescription: simple class instantiation testshould_fail: 0tags: 8.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: instantiationdescription: simple class instantiation testshould_fail: 0tags: 8.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.4--instantiation.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') test_cls test_obj;
name: properties_enumdescription: enum defined inside classshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:12:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:15:14: error: language feature not yet supported test_obj = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:16:12: error: use of undeclared identifier 'test_cls' $display(test_cls.C); ^~~~~~~~
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8:2: error: language feature not yet supported class test_cls #(parameter a = 12); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:11:2: error: language feature not yet supported test_cls #(34) test_obj; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14:14: error: language feature not yet supported test_obj = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:15:12: error: use of undeclared identifier 'test_cls' $display(test_cls.a); ^~~~~~~~
name: propertiesdescription: class properties testshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:12:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:15:14: error: language feature not yet supported test_obj = new; ^~~
name: properties_enumdescription: enum defined inside classshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:15: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: syntax error, unexpected parameter, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv
name: propertiesdescription: class properties testshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:15: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv
name: properties_enumdescription: enum defined inside classshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: syntax error, unexpected '#', expecting '(' or '['
name: propertiesdescription: class properties testshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: properties_enumdescription: enum defined inside classshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv::9 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum {A = 10, B = 20, C = 30, D = 1} e_type;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties_enum.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') test_cls test_obj;
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::8 error in parsing: (syntax error, unexpected '#', expecting '(') class test_cls #(parameter a = 12);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::11 error in parsing: (syntax error, unexpected '#', expecting '(') test_cls #(34) test_obj;
name: propertiesdescription: class properties testshould_fail: 0tags: 8.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--properties.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') test_cls test_obj;
name: methodsdescription: class method testshould_fail: 0tags: 8.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:16:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:19:14: error: language feature not yet supported test_obj = new; ^~~
name: methodsdescription: class method testshould_fail: 0tags: 8.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:19: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv
name: methodsdescription: class method testshould_fail: 0tags: 8.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: methodsdescription: class method testshould_fail: 0tags: 8.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task test_method(int val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.6--methods.sv::12 error in parsing: (syntax error, unexpected '+', expecting vSYMBOL_ID or '#') a += val;
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 13 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv
name: constructor_paramdescription: class constructor with arguments testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv
name: constructordescription: class constructor testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: constructor_paramdescription: class constructor with arguments testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: constructordescription: class constructor testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 3);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::15 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::16 Function already has output with this name new function new(int def = 42);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: constructor_paramdescription: class constructor with arguments testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 42);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv::19 error in parsing: (syntax error, unexpected vEND) endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: constructordescription: class constructor testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv::15 error in parsing: (syntax error, unexpected vINITIAL, expecting vSYMBOL_ID or '#') initial beginPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor.sv::19 error in parsing: (syntax error, unexpected vEND) endERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 0
name: constructor_paramdescription: class constructor with arguments testshould_fail: 0tags: 8.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv']incdirs: []top_module: rc: 6/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:16: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:16: error: malformed statement/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:18: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:18: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_param.sv:19: syntax errorI give up.
name: typed_constructordescription: class typed constructor testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:17: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:26: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:26: Perhaps 'test_cls' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 15 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv
name: typed_constructor_paramdescription: typed class constructor with parameters testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:17: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:26: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv
name: typed_constructordescription: class typed constructor testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: typed_constructor_paramdescription: typed class constructor with parameters testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: typed_constructordescription: class typed constructor testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 3);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::16 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor.sv::17 Function already has output with this name new function new(int def = 42);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: typed_constructor_paramdescription: typed class constructor with parameters testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 3);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::16 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv::17 Function already has output with this name new function new(int def = 42);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: typed_constructor_paramdescription: typed class constructor with parameters testshould_fail: 0tags: 8.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.8--typed_constructor_param.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: static_propertiesdescription: static class properties testshould_fail: 0tags: 8.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv:12:2: error: use of undeclared identifier 'test_cls' test_cls test_obj0; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv:13:2: error: use of undeclared identifier 'test_cls' test_cls test_obj1; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv:16:15: error: language feature not yet supported test_obj0 = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.9--static_properties.sv:17:15: error: language feature not yet supported test_obj1 = new; ^~~
name: static_methodsdescription: static class methods testshould_fail: 0tags: 8.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:15:2: error: use of undeclared identifier 'test_cls' test_cls test_obj0; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:16:2: error: use of undeclared identifier 'test_cls' test_cls test_obj1; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:19:15: error: language feature not yet supported test_obj0 = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:20:15: error: language feature not yet supported test_obj1 = new; ^~~
name: static_methodsdescription: static class methods testshould_fail: 0tags: 8.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:10: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:10: syntax error, unexpected function, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:19: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:20: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 10 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv
name: static_methodsdescription: static class methods testshould_fail: 0tags: 8.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: static_methodsdescription: static class methods testshould_fail: 0tags: 8.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') static int id = 0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::16 error in parsing: (syntax error, unexpected ';', expecting '(') test_cls test_obj1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::22 error in parsing: (syntax error, unexpected ')') $display(test_obj0.next_id());PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.10--static_methods.sv::23 error in parsing: (syntax error, unexpected ')') $display(test_obj1.next_id());ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: thisdescription: this keyword testshould_fail: 0tags: 8.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~
name: thisdescription: this keyword testshould_fail: 0tags: 8.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: this%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:12: syntax error, unexpected '.'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv
name: thisdescription: this keyword testshould_fail: 0tags: 8.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: thisdescription: this keyword testshould_fail: 0tags: 8.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task test_method(int a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.11--this.sv::12 error in parsing: (syntax error, unexpected '+', expecting vSYMBOL_ID or '#') this.a += a;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: assignmentdescription: object assignmentshould_fail: 0tags: 8.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--assignment.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--assignment.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--assignment.sv:16:2: error: use of undeclared identifier 'test_cls' test_cls test_obj0; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--assignment.sv:17:2: error: use of undeclared identifier 'test_cls' test_cls test_obj1; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--assignment.sv:20:15: error: language feature not yet supported test_obj0 = new; ^~~
name: shallow_copydescription: object shallow copyshould_fail: 0tags: 8.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv:16:2: error: use of undeclared identifier 'test_cls' test_cls test_obj0; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv:17:2: error: use of undeclared identifier 'test_cls' test_cls test_obj1; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv:20:15: error: language feature not yet supported test_obj0 = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.12--shallow_copy.sv:26:15: error: language feature not yet supported test_obj1 = new test_obj0; ^~~~~~~~~~~~~
name: inheritancedescription: class inheritance testshould_fail: 0tags: 8.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:11: syntax error, unexpected ++, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:13: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:20: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv
name: inheritancedescription: class inheritance testshould_fail: 0tags: 8.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: inheritancedescription: class inheritance testshould_fail: 0tags: 8.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function int incs();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::19 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::20 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 42);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::31 error in parsing: (syntax error, unexpected ')') $display(test_obj.incs());PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.13--inheritance.sv::33 error in parsing: (syntax error, unexpected vEND) endERROR (10)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: override_memberdescription: class member override testshould_fail: 0tags: 8.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:8:2: error: language feature not yet supported class super_cls; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:13:11: error: expected identifier function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:13:12: error: expected statement function new(int def = 3); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:13:27: error: expected declarator function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:18:2: error: language feature not yet supported class test_cls extends super_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:24:11: error: expected identifier function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:24:12: error: expected statement function new(int def = 42); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:24:28: error: expected declarator function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:30:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:31:2: error: use of undeclared identifier 'super_cls' super_cls super_obj; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:34:14: error: language feature not yet supported test_obj = new(37); ^~~~~~~
name: override_memberdescription: class member override testshould_fail: 0tags: 8.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv']incdirs: []top_module: rc: 0
name: override_memberdescription: class member override testshould_fail: 0tags: 8.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:11: syntax error, unexpected ++, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:13: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:24: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:28: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 14 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv
name: override_memberdescription: class member override testshould_fail: 0tags: 8.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: override_memberdescription: class member override testshould_fail: 0tags: 8.14files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function int incs();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::19 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.14--override_member.sv::20 Function already has output with this name int function int incs();Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: superdescription: accessing superclass methods via supershould_fail: 0tags: 8.15files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:11: syntax error, unexpected ++, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:13: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:22: syntax error, unexpected '.', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:24: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:28: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 16 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv
name: superdescription: accessing superclass methods via supershould_fail: 0tags: 8.15files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: superdescription: accessing superclass methods via supershould_fail: 0tags: 8.15files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function int incs();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::19 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.15--super.sv::20 Function already has output with this name int function int incs();Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: cast_funcdescription: $cast function testshould_fail: 0tags: 8.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv:11: Unsupported or unknown PLI call: $cast%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv
name: cast_taskdescription: $cast task testshould_fail: 0tags: 8.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv:11: Unsupported or unknown PLI call: $cast%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv
name: cast_funcdescription: $cast function testshould_fail: 0tags: 8.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv:8: syntax error, unexpected '{', expecting '(' or '['
name: cast_funcdescription: $cast function testshould_fail: 0tags: 8.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum { aaa, bbb, ccc, ddd, eee } values;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') values val;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_func.sv::14 error in parsing: (syntax error, unexpected vEND) endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: cast_taskdescription: $cast task testshould_fail: 0tags: 8.16files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv::8 error in parsing: (syntax error, unexpected '{', expecting '(') typedef enum { aaa, bbb, ccc, ddd, eee } values;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') values val;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.16--cast_task.sv::13 error in parsing: (syntax error, unexpected vEND) endERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8:2: error: language feature not yet supported class super_cls; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10:11: error: expected identifier function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10:12: error: expected statement function new(int def = 3); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10:27: error: expected declarator function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:14:2: error: language feature not yet supported class test_cls extends super_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16:11: error: expected identifier function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16:12: error: expected statement function new(int def = 42); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16:28: error: expected declarator function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:22:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:25:14: error: language feature not yet supported test_obj = new(37); ^~~~~~~
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:8:2: error: language feature not yet supported class super_cls; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:10:11: error: expected identifier function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:10:12: error: expected statement function new(int def = 3); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:10:27: error: expected declarator function new(int def = 3); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:14:2: error: language feature not yet supported class test_cls extends super_cls(5); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:16:11: error: expected identifier function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:16:12: error: expected statement function new(int def = 42); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:16:28: error: expected declarator function new(int def = 42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:21:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:24:14: error: language feature not yet supported test_obj = new(37); ^~~~~~~
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 0
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 0
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:16: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: super%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 13 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:16: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 3);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::15 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv::16 Function already has output with this name new function new(int def = 42);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int s = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int def = 3);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::15 error in parsing: (syntax error, unexpected ';', expecting '(') int a;ERROR (7)::PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv::16 Function already has output with this name new function new(int def = 42);Assertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/parse_making_ast.cpp]markAndProcessPortWith::522
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 0
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 0
name: constructor_superdescription: class constructor super testshould_fail: 0tags: 8.7 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.7--constructor_super.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: constructor_const_argdescription: class inheritance with a constant constructor argumentshould_fail: 0tags: 8.17files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.17--constructor_const_arg.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: inherited_prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: local_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: inherited_prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: inherited_local_from_insidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: inherited_local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:8:1: error: language feature not yet supportedclass a_cls;^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:13:1: error: language feature not yet supportedclass b_cls extends a_cls;^~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:21:1: error: use of undeclared identifier 'b_cls'b_cls b_obj;^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:23:13: error: language feature not yet supported b_obj = new; ^~~
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:8:2: error: language feature not yet supported class a_cls; ^~~~~~~~~~~~
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:8:2: error: language feature not yet supported class a_cls; ^~~~~~~~~~~~
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 0
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 0
name: inherited_prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv
name: local_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv
name: inherited_prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv
name: inherited_local_from_insidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv
name: local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv
name: prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv
name: inherited_local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv
name: prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv:23: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: protected%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: local%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: inherited_prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_inside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: local_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_inside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: inherited_prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_prot_from_outside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: inherited_local_from_insidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_inside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: prot_from_insidedescription: encapsulation testshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_inside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: inherited_local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: prot_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(')class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 21;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 22;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')class b_cls extends a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int b_loc = 31;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int b_prot = 32;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int b = 33;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--prot_from_outside.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') protected int a_prot = 2;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') local int a_loc = 2;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--local_from_outside.sv:24: error: Local property b_loc is not accessible in this context. (scope=top)1 error(s) during elaboration.
name: inherited_local_from_outsidedescription: encapsulation testshould_fail: 1tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/generated/encapsulation/8.18--inherited_local_from_outside.sv:24: error: Local property a_loc is not accessible in this context. (scope=top)1 error(s) during elaboration.
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 0
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 0
name: var_protecteddescription: class with protected variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_protected.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: var_localdescription: class with local variableshould_fail: 0tags: 8.18files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.18--var_local.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:8:2: error: language feature not yet supported class a_cls; ^~~~~~~~~~~~
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:8:2: error: language feature not yet supported class a_cls; ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:10:11: error: expected identifier function new(int val); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:10:12: error: expected statement function new(int val); ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:10:23: error: expected declarator function new(int val); ^
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 0
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 0
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:10: syntax error, unexpected '(', expecting '['%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') const int c = 12;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class a_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') const int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vINPUT or ')') function new(int val);ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 0
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 0
name: global_constantdescription: class with global constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--global_constant.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: instance_constantdescription: class with instance constant variableshould_fail: 0tags: 8.19files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.19--instance_constant.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:8:2: error: language feature not yet supported class super_cls; ^~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:15:2: error: language feature not yet supported class test_cls extends super_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:22:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:23:2: error: use of undeclared identifier 'super_cls' super_cls super_obj; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:26:14: error: language feature not yet supported test_obj = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:27:15: error: language feature not yet supported super_obj = new; ^~~
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 0
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:26: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:27: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 12 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class super_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::12 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::16 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv::23 error in parsing: (syntax error, unexpected ';', expecting '(') super_cls super_obj;
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:32: internal_error: net type doesn't match context type./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:32: : net type=class test_cls{bool signed[31:0] a}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:32: : context type=class super_cls{bool signed[31:0] a}/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:32: assert: elab_expr.cc:3470: failed assertion ntype->type_compatible(net->net_type())Aborted (core dumped)
name: virtual_methoddescription: class with virtual methodsshould_fail: 0tags: 8.20files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.20--virtual_method.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: abstract_classdescription: class extending abstract classshould_fail: 0tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:8:2: error: language feature not yet supported virtual class base_cls; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:12:2: error: language feature not yet supported class test_cls extends base_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:19:2: error: use of undeclared identifier 'test_cls' test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:22:14: error: language feature not yet supported test_obj = new; ^~~
name: abstract_class_instdescription: instantiating abstract classshould_fail: 1tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:8:2: error: language feature not yet supported virtual class base_cls; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:12:2: error: language feature not yet supported class test_cls extends base_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:19:2: error: use of undeclared identifier 'base_cls' base_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:22:14: error: language feature not yet supported test_obj = new; ^~~
name: abstract_classdescription: class extending abstract classshould_fail: 0tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv
name: abstract_class_instdescription: instantiating abstract classshould_fail: 1tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 11 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv
name: abstract_classdescription: class extending abstract classshould_fail: 0tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: abstract_classdescription: class extending abstract classshould_fail: 0tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') virtual class base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void print();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class test_cls extends base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::13 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: abstract_class_instdescription: instantiating abstract classshould_fail: 1tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') virtual class base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void print();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class test_cls extends base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::13 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class_inst.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: abstract_classdescription: class extending abstract classshould_fail: 0tags: 8.21files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.21--abstract_class.sv:9: error: invalid class item.
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:8:2: error: language feature not yet supported virtual class base_cls; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:12:2: error: language feature not yet supported class a_cls extends base_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:18:2: error: language feature not yet supported class b_cls extends base_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:24:2: error: language feature not yet supported class c_cls extends base_cls; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:30:2: error: use of undeclared identifier 'base_cls' base_cls arr[3]; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:31:2: error: use of undeclared identifier 'a_cls' a_cls a; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:32:2: error: use of undeclared identifier 'b_cls' b_cls b; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:33:2: error: use of undeclared identifier 'c_cls' c_cls c; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:36:7: error: language feature not yet supported a = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:37:7: error: language feature not yet supported b = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:38:7: error: language feature not yet supported c = new; ^~~
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: 0
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:28: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:36: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:36: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:37: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:37: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:38: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:38: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 23 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') virtual class base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void print();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class a_cls extends base_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::15 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::21 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::27 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::31 error in parsing: (syntax error, unexpected ';', expecting '(') a_cls a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::32 error in parsing: (syntax error, unexpected ';', expecting '(') b_cls b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::33 error in parsing: (syntax error, unexpected ';', expecting '(') c_cls c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv::43 error in parsing: (syntax error, unexpected '.', expecting voLTE or '=') arr[0].print();ERROR (13)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: dynamic_method_lookupdescription: dynamic method selection with abstract base classshould_fail: 0tags: 8.22files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.22--dynamic_method_lookup.sv:9: error: invalid class item.
name: scope_resolutiondescription: access static method using scope resolution operatorshould_fail: 0tags: 8.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:16:12: error: unknown class or package 'test_cls' $display(test_cls::next_id()); ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:17:12: error: unknown class or package 'test_cls' $display(test_cls::next_id()); ^~~~~~~~
name: scope_resolutiondescription: access static method using scope resolution operatorshould_fail: 0tags: 8.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:9: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:10: Unsupported: Static in this context%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:10: syntax error, unexpected function, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv
name: scope_resolutiondescription: access static method using scope resolution operatorshould_fail: 0tags: 8.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: scope_resolutiondescription: access static method using scope resolution operatorshould_fail: 0tags: 8.23files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') static int id = 0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.23--scope_resolution.sv::17 error in parsing: (syntax error, unexpected ':', expecting ')') $display(test_cls::next_id());ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: out_of_block_methodsdescription: out-of-body method declarationshould_fail: 0tags: 8.24files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:8:2: error: language feature not yet supported class test_cls; ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:15:3: error: use of undeclared identifier 'a' a += val; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:18:2: error: 'test_cls' is not a type test_cls test_obj; ^~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:21:14: error: language feature not yet supported test_obj = new; ^~~
name: out_of_block_methodsdescription: out-of-body method declarationshould_fail: 0tags: 8.24files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv::8 error in parsing: (syntax error, unexpected ';', expecting '(') class test_cls;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv::15 error in parsing: (syntax error, unexpected '+', expecting vSYMBOL_ID or '#') a += val;
name: out_of_block_methodsdescription: out-of-body method declarationshould_fail: 0tags: 8.24files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv']incdirs: []top_module: rc: 3/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:10: sorry: External methods are not yet supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.24--out_of_block_methods.sv:13: error: I give up on this function definition.
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8:2: error: language feature not yet supported class test_cls #(parameter a = 12); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:11:2: error: language feature not yet supported test_cls #(34) test_obj; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14:14: error: language feature not yet supported test_obj = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:15:12: error: use of undeclared identifier 'test_cls' $display(test_cls.a); ^~~~~~~~
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:8:2: error: language feature not yet supported class base_cls #(int b = 20); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:12:2: error: language feature not yet supported class ext_cls #(int e = 25) extends base_cls(5); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:16:2: error: language feature not yet supported ext_cls #(15) inst; ^~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:19:10: error: language feature not yet supported inst = new; ^~~
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: 0
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: syntax error, unexpected parameter, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:14: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 5 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:8: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:12: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:19: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 9 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv:8: syntax error, unexpected '#', expecting '(' or '['
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:8: syntax error, unexpected '#', expecting '(' or '['
name: parametersdescription: parametrized class testshould_fail: 0tags: 8.5 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::8 error in parsing: (syntax error, unexpected '#', expecting '(') class test_cls #(parameter a = 12);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.5--parameters.sv::11 error in parsing: (syntax error, unexpected '#', expecting '(') test_cls #(34) test_obj;
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::8 error in parsing: (syntax error, unexpected '#', expecting '(') class base_cls #(int b = 20);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(') int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class ext_cls #(int e = 25) extends base_cls(5);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::13 error in parsing: (syntax error, unexpected ';', expecting '(') int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv::16 error in parsing: (syntax error, unexpected '#', expecting '(') ext_cls #(15) inst;
name: parametrized_class_extenddescription: parametrized class extending another parametrized classshould_fail: 0tags: 8.25files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25--parametrized_class_extend.sv:8:9: Parse error: unexpected token 'class' (KW_class).
name: parametrized_class_scope_resolutiondescription: parametrized class scope resolutionshould_fail: 0tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:9:2: error: language feature not yet supported class par_cls #(int a = 25); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:13:2: error: language feature not yet supported par_cls #(15) inst; ^~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:16:10: error: language feature not yet supported inst = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:18:12: error: language feature not yet supported $display(par_cls#()::b); ^~~~~~~~~~~~~
name: parametrized_class_invalid_scope_resolutiondescription: parametrized class invalid scope resolutionshould_fail: 1tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:9:2: error: language feature not yet supported class par_cls #(int a = 25); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:13:2: error: language feature not yet supported par_cls #(15) inst; ^~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:16:10: error: language feature not yet supported inst = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:18:12: error: unknown class or package 'par_cls' $display(par_cls::b); ^~~~~~~
name: parametrized_class_scope_resolutiondescription: parametrized class scope resolutionshould_fail: 0tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:9: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:16: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:18: syntax error, unexpected '#', expecting ')' or ','%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv
name: parametrized_class_invalid_scope_resolutiondescription: parametrized class invalid scope resolutionshould_fail: 1tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:9: syntax error, unexpected IDENTIFIER, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:16: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:18: syntax error, unexpected ::, expecting ')' or ','%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:18: Perhaps 'par_cls' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv
name: parametrized_class_scope_resolutiondescription: parametrized class scope resolutionshould_fail: 0tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv:9: syntax error, unexpected '#', expecting '(' or '['
name: parametrized_class_invalid_scope_resolutiondescription: parametrized class invalid scope resolutionshould_fail: 1tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv:9: syntax error, unexpected '#', expecting '(' or '['
name: parametrized_class_scope_resolutiondescription: parametrized class scope resolutionshould_fail: 0tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv::9 error in parsing: (syntax error, unexpected '#', expecting '(') class par_cls #(int a = 25);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') parameter int b = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv::13 error in parsing: (syntax error, unexpected '#', expecting '(') par_cls #(15) inst;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_scope_resolution.sv::18 error in parsing: (syntax error, unexpected '#', expecting ')') $display(par_cls#()::b);ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: parametrized_class_invalid_scope_resolutiondescription: parametrized class invalid scope resolutionshould_fail: 1tags: 8.25.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv::9 error in parsing: (syntax error, unexpected '#', expecting '(') class par_cls #(int a = 25);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';' or ',') parameter int b = 23;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv::13 error in parsing: (syntax error, unexpected '#', expecting '(') par_cls #(15) inst;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.25.1--parametrized_class_invalid_scope_resolution.sv::18 error in parsing: (syntax error, unexpected ':', expecting ')') $display(par_cls::b);ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7:1: error: language feature not yet supportedinterface class base_ic extends basebase;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:7:1: error: language feature not yet supportedinterface class base_ic #(int N = 8, type T = string);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7:1: error: language feature not yet supportedinterface class base_ic extends base1, base2, base3;^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7:1: error: language feature not yet supportedinterface class base_ic #(int N = 8) extends pkg1::base1, base2#(N);^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:7:1: error: language feature not yet supportedinterface class base_ic;^~~~~~~~~~~~~~~~~~~~~~~~
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv:8: syntax error, unexpected ':'%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:9: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv:9: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:8: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:10: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:11: syntax error, unexpected '#', expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:8: syntax error, unexpected '[', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv:11: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:10: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:10: Perhaps 'bhg' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:8: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:7: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:8: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:7: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv:9: syntax error, unexpected $end%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv
name: iface_class_test_3description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_3.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic extends basebase;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_1description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_1.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_11description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_11.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_2description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_2.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic #(int N = 8, type T = string);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_7description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_7.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_6description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_6.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_8description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_8.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_9description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_9.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_4description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_4.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic extends base1, base2, base3;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_5description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_5.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic #(int N = 8) extends pkg1::base1, base2#(N);ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_10description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_10.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: iface_class_test_0description: Testshould_fail: 0tags: 8.3 8.26files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generic/iface/iface_class_test_0.sv::7 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vMODULE or preDEFAULT_NETTYPE)interface class base_ic;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: implements_multipledescription: class implementing multiple interfacesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:12:2: error: language feature not yet supported interface class itest; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:16:2: error: language feature not yet supported class Hello implements ihello, itest; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:25:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:28:9: error: language feature not yet supported obj = new; ^~~
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:12:2: error: language feature not yet supported interface class itest; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:16:2: error: language feature not yet supported class Hello implements ihello, itest; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:25:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:26:2: error: use of undeclared identifier 'ihello' ihello ih_ref; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:27:2: error: use of undeclared identifier 'itest' itest it_ref; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:30:9: error: language feature not yet supported obj = new; ^~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:32:3: error: use of undeclared identifier '$cast' $cast(it_ref, ih_ref); ^~~~~
name: implementsdescription: implements keyword testshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:12:2: error: language feature not yet supported class Hello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:18:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:21:9: error: language feature not yet supported obj = new; ^~~
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:12:2: error: language feature not yet supported interface class itest; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:16:2: error: language feature not yet supported class base; ^~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:22:2: error: language feature not yet supported class Hello extends base implements ihello, itest; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:31:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:34:9: error: language feature not yet supported obj = new; ^~~
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: 0
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: 0
name: implements_multipledescription: class implementing multiple interfacesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:16: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:28: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:28: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 14 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:16: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:30: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:30: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:32: Unsupported or unknown PLI call: $cast%Error: Exiting due to 15 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv
name: implementsdescription: implements keyword testshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:12: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv:21: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 10 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:22: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:22: syntax error, unexpected IDENTIFIER, expecting ',' or ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:34: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:34: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 18 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv
name: implements_multipledescription: class implementing multiple interfacesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: implements_multipledescription: class implementing multiple interfacesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void test();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello, itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_multiple.sv::22 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void test();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello, itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::22 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::26 error in parsing: (syntax error, unexpected ';', expecting '(') ihello ih_ref;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv::27 error in parsing: (syntax error, unexpected ';', expecting '(') itest it_ref;
name: implementsdescription: implements keyword testshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements.sv::15 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void test();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class base;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::22 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello extends base implements ihello, itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::25 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv::28 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: cast_between_interface_classesdescription: it should be possible to cast between implemented interface classesshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--cast_between_interface_classes.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: implements_extendsdescription: class both implementing and extendingshould_fail: 0tags: 8.26.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.2--implements_extends.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: type_access_implements_invaliddescription: access types from implemented classshould_fail: 1tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:13:2: error: language feature not yet supported class Hello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:19:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:22:9: error: language feature not yet supported obj = new; ^~~
name: type_access_implementsdescription: access interface class type with scope resolution operatorshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:13:2: error: language feature not yet supported class Hello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:19:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:22:9: error: language feature not yet supported obj = new; ^~~
name: type_access_extendsdescription: accessing types from extended interface classshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:13:2: error: language feature not yet supported interface class ihello_ex extends ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: type_access_implements_invaliddescription: access types from implemented classshould_fail: 1tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:10: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:13: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 11 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv
name: type_access_implementsdescription: access interface class type with scope resolution operatorshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:10: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:13: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:14: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:14: Perhaps 'ihello' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:7: ../V3ParseSym.h:112: Symbols suggest ending TASK 'hello' but parser thinks ending MODULE 'class_tb'%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv
name: type_access_extendsdescription: accessing types from extended interface classshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:10: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 9 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv
name: type_access_implements_invaliddescription: access types from implemented classshould_fail: 1tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: type_access_implementsdescription: access interface class type with scope resolution operatorshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: type_access_extendsdescription: accessing types from extended interface classshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: type_access_implements_invaliddescription: access types from implemented classshould_fail: 1tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int int_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::10 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello(int_t val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements_invalid.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: type_access_implementsdescription: access interface class type with scope resolution operatorshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int int_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::10 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello(int_t val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_implements.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: type_access_extendsdescription: accessing types from extended interface classshould_fail: 0tags: 8.26.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int int_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::10 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello(int_t val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello_ex extends ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.3--type_access_extends.sv::14 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello_ex(int_t v1, int_t v2);ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:13:2: error: language feature not yet supported class Hello #(type T = ihello) implements T; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:19:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:22:9: error: language feature not yet supported obj = new; ^~~
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:8:26: error: forward typedef 'ihello' does not resolve to a data type typedef interface class ihello; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:10:2: error: language feature not yet supported class Hello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:16:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:21:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:24:9: error: language feature not yet supported obj = new; ^~~
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 0
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: 0
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:10: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:13: syntax error, unexpected type, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:13: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:14: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:14: Perhaps 'ihello' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:7: ../V3ParseSym.h:112: Symbols suggest ending TASK 'hello' but parser thinks ending MODULE 'class_tb'%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:8: syntax error, unexpected interface, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:10: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:11: syntax error, unexpected ::, expecting ')'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:11: Perhaps 'ihello' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:18: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:24: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:7: ../V3ParseSym.h:112: Symbols suggest ending TASK 'hello' but parser thinks ending MODULE 'class_tb'%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int int_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::10 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello(int_t val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello #(type T = ihello) implements T;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::13 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef int int_t;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::18 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello(int_t val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv::21 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') Hello obj;
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 12/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:10: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:13: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:14: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:15: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:16: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:19: error: invalid module item.
name: illegal_implements_parameterdescription: implementing parameter that resolves to an interface class is not allowedshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_implements_parameter.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: illegal_forward_def_implementsdescription: implementing forward typedef for an interface class should failshould_fail: 1tags: 8.26.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.4--illegal_forward_def_implements.sv:8:17: Parse error: unexpected token 'interface' (KW_interface).
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:12:2: error: language feature not yet supported class Hello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:18:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:19:2: error: use of undeclared identifier 'ihello' ihello iobj; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:22:9: error: language feature not yet supported obj = new; ^~~
name: interface_instantiationdescription: instantiating an interface classshould_fail: 1tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:12:2: error: use of undeclared identifier 'ihello' ihello obj; ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:15:9: error: language feature not yet supported obj = new; ^~~
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 0
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:12: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:22: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 10 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv
name: interface_instantiationdescription: instantiating an interface classshould_fail: 1tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:15: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:15: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 6 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: interface_instantiationdescription: instantiating an interface classshould_fail: 1tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::15 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv::19 error in parsing: (syntax error, unexpected ';', expecting '(') ihello iobj;
name: interface_instantiationdescription: instantiating an interface classshould_fail: 1tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--invalid_interface_instantiation.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') ihello obj;
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 14/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:9: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:13: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:14: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:15: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:18: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:19: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:19: error: Invalid module instantiation
name: implemented_class_handledescription: it should be possible to assign object handle to a variable of an implemented class typeshould_fail: 0tags: 8.26.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.5--implemented_class_handle.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:12:2: error: language feature not yet supported interface class itest; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:16:2: error: language feature not yet supported class Hello implements ihello, itest; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:22:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:25:9: error: language feature not yet supported obj = new; ^~~
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:12:2: error: language feature not yet supported interface class itest; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:16:2: error: language feature not yet supported class Hello implements ihello, itest; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:22:2: error: use of undeclared identifier 'Hello' Hello obj; ^~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:25:9: error: language feature not yet supported obj = new; ^~~
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: 0
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: 0
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:16: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:25: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 13 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:16: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:25: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 13 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function int hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello, itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class Hello implements ihello, itest;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv::19 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: name_conflict_unresolveddescription: unresolved interface class method name conflictshould_fail: 1tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_unresolved.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: name_conflict_resolveddescription: resolved interface class method name conflictshould_fail: 0tags: 8.26.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.1--name_conflict_resolved.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8:2: error: language feature not yet supported interface class ic1#(type T = logic); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:12:2: error: language feature not yet supported interface class ic2#(type T = logic); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:16:2: error: language feature not yet supported interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:8:2: error: language feature not yet supported interface class ic1#(type T = logic); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:12:2: error: language feature not yet supported interface class ic2#(type T = logic); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:16:2: error: language feature not yet supported interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 0
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: 0
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:17: syntax error, unexpected IDENTIFIER, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 11 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 10 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic1#(type T = logic);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn1(T a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic2#(type T = logic);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn2(T a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef TYPE T;ERROR (9)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic1#(type T = logic);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn1(T a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic2#(type T = logic);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn2(T a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic3#(type TYPE = logic) extends ic1#(TYPE), ic2#(TYPE);ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 14/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:9: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:13: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:16: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:17: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:17: error: Syntax error in typedef clause./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:18: syntax errorI give up.
name: parameter_type_conflictdescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 0tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: parameter_type_conflict_unresolveddescription: superclass type declaration conflicts must be resolved in subclassshould_fail: 1tags: 8.26.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.2--parameter_type_conflict_unresolved.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:8:2: error: language feature not yet supported interface class ibase; ^~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:12:2: error: language feature not yet supported interface class ic1 extends ibase; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:16:2: error: language feature not yet supported interface class ic2 extends ibase; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:20:2: error: language feature not yet supported interface class ic3 extends ic1, ic2; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8:2: error: language feature not yet supported interface class ibase#(type T = logic); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:12:2: error: language feature not yet supported interface class ic1 extends ibase#(bit); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:16:2: error: language feature not yet supported interface class ic2 extends ibase#(string); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:20:2: error: language feature not yet supported interface class ic3 extends ic1, ic2; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: 0
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 0
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 16 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 16 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ibase;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic1 extends ibase;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn1();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic2 extends ibase;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::17 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn2();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::20 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic3 extends ic1, ic2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv::21 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn3();ERROR (11)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ibase#(type T = logic);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn(T val);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic1 extends ibase#(bit);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::13 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn1();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic2 extends ibase#(string);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::17 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn2();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::20 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ic3 extends ic1, ic2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv::21 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void fn3();ERROR (11)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 18/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:9: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:10: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:13: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:16: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:17: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:17: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:18: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:20: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:21: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:21: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:22: syntax errorI give up.
name: diamond_relationshipdescription: interface class inherited from multiple sources shouldn't create symbol conflictsshould_fail: 0tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: diamond_relationship_parametrizeddescription: different specializations of an interface class are treated as unique interface class typesshould_fail: 1tags: 8.26.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.6.3--diamond_relationship_parametrized.sv:8:9: Parse error: unexpected token 'interface' (KW_interface).
name: partial_implementationdescription: virtual classes can implement their interfaces partiallyshould_fail: 0tags: 8.26.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:8:2: error: language feature not yet supported interface class ihello; ^~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:13:2: error: language feature not yet supported virtual class vhello implements ihello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:20:2: error: language feature not yet supported class helloworld extends vhello; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:26:2: error: use of undeclared identifier 'helloworld' helloworld obj; ^~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:29:9: error: language feature not yet supported obj = new; ^~~
name: partial_implementationdescription: virtual classes can implement their interfaces partiallyshould_fail: 0tags: 8.26.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv']incdirs: []top_module: rc: 0
name: partial_implementationdescription: virtual classes can implement their interfaces partiallyshould_fail: 0tags: 8.26.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:8: syntax error, unexpected interface%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:11: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:13: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:13: Unsupported: SystemVerilog 2012 reserved word not implemented: implements%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:17: syntax error, unexpected pure%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: extends%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: virtual%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:29: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:29: syntax error, unexpected ';', expecting TYPE-IDENTIFIER%Error: Exiting due to 18 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv
name: partial_implementationdescription: virtual classes can implement their interfaces partiallyshould_fail: 0tags: 8.26.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: partial_implementationdescription: virtual classes can implement their interfaces partiallyshould_fail: 0tags: 8.26.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') interface class ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::9 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void hello();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::10 error in parsing: (syntax error, unexpected vFUNCTION, expecting '(') pure virtual function void world();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::13 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') virtual class vhello implements ihello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::16 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunctionPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::20 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class helloworld extends vhello;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.26.7--partial_implementation.sv::23 error in parsing: (syntax error, unexpected vENDFUNCTION) endfunction
name: forward_declarationdescription: class forward declaration testshould_fail: 0tags: 8.27files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:8:16: error: forward typedef 'C2' does not resolve to a data type typedef class C2; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:10:2: error: language feature not yet supported class C1; ^~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:14:2: error: language feature not yet supported class C2; ^~~~~~~~~
name: forward_declarationdescription: class forward declaration testshould_fail: 0tags: 8.27files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:8: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:10: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:10: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: class%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:14: syntax error, unexpected ';', expecting IDENTIFIER or do or final%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endclass%Error: Exiting due to 7 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv
name: forward_declarationdescription: class forward declaration testshould_fail: 0tags: 8.27files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv:8: syntax error, unexpected TOK_ID, expecting '(' or '['
name: forward_declarationdescription: class forward declaration testshould_fail: 0tags: 8.27files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef class C2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(') class C1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(') C2 c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') class C2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-8/8.27--forward_declaration.sv::15 error in parsing: (syntax error, unexpected ';', expecting '(') C1 c;ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: initialdescription: initial checkshould_fail: 0tags: 9.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.1--initial.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.1--initial.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.1--initial.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: alwaysdescription: always checkshould_fail: 0tags: 9.2.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: alwaysdescription: always checkshould_fail: 0tags: 9.2.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: alwaysdescription: always checkshould_fail: 0tags: 9.2.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.1--always.sv']incdirs: []top_module: rc: 0module always_tb; wire a = 0; reg b = 0; always b = (~ a);endmodule
name: always_combdescription: always_comb checkshould_fail: 0tags: 9.2.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.2--always_comb.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.2--always_comb.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.2--always_comb.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.2--always_comb.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(') b = ~a;
name: always_latchdescription: always_latch checkshould_fail: 0tags: 9.2.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.3--always_latch.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.3--always_latch.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.3--always_latch.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.3--always_latch.sv::12 error in parsing: (syntax error, unexpected vIF, expecting vSYMBOL_ID or '#') if(a) q <= b;
name: always_ffdescription: always_ff checkshould_fail: 0tags: 9.2.2.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.4--always_ff.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.4--always_ff.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.4--always_ff.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.4--always_ff.sv::11 error in parsing: (syntax error, unexpected '@', expecting vSYMBOL_ID or '#') always_ff @(posedge a)
name: always_ffdescription: always_ff checkshould_fail: 0tags: 9.2.2.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.2.4--always_ff.sv']incdirs: []top_module: rc: 0module always_tb; wire a = 0; wire b = 0; reg q = 0; always @(posedge a) q <= b;endmodule
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: 0
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: 0
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: 0
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv:10: syntax error, unexpected '=', expecting '(' or '['
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(') a = 1;
name: finaldescription: final checkshould_fail: 0tags: 9.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.2.3--final.sv']incdirs: []top_module: rc: 0
name: sequential_blockdescription: sequential block checkshould_fail: 0tags: 9.3.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.1--sequential_block.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.1--sequential_block.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.1--sequential_block.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: parallel_block_join_nonedescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv:14: syntax error, unexpected '=', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv
name: parallel_block_join_anydescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv:14: syntax error, unexpected '=', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: join_any%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv
name: parallel_block_joindescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv:14: syntax error, unexpected '=', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv:16: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv
name: parallel_block_join_nonedescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_none.sv::14 error in parsing: (syntax error, unexpected '=', expecting vSYMBOL_ID or '#') b = 0;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: parallel_block_join_anydescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join_any.sv::14 error in parsing: (syntax error, unexpected '=', expecting vSYMBOL_ID or '#') b = 0;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: parallel_block_joindescription: parallel block checkshould_fail: 0tags: 9.3.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv::14 error in parsing: (syntax error, unexpected '=', expecting vSYMBOL_ID or '#') b = 0;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.2--parallel_block_join.sv::16 Unsuported token join ^~~~
name: fork_returndescription: illegal return from forkshould_fail: 1tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv:9: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv:10: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv:12: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv
name: event_orderdescription: event order testshould_fail: 0tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:8: Unsupported: Verilog 1995 reserved word not implemented: event%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:8: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:10: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:14: syntax error, unexpected ->%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:20: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv
name: block_start_finishdescription: block start finish checkshould_fail: 0tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:10: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:11: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:12: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:14: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:15: Unsupported: Verilog 1995 reserved word not implemented: join%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:17: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:18: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:19: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:20: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:21: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv:22: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv
name: fork_returndescription: illegal return from forkshould_fail: 1tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv:13: syntax error, unexpected TOK_ENDTASK
name: event_orderdescription: event order testshould_fail: 0tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv:8: syntax error, unexpected ';', expecting '(' or '['
name: fork_returndescription: illegal return from forkshould_fail: 1tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv::9 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv::10 error in parsing: (syntax error, unexpected vDELAY_ID) #20;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_orderdescription: event order testshould_fail: 0tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::8 Unsuported token event ev; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::8 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') event ev;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::10 Unsuported token initial fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::13 error in parsing: (syntax error, unexpected vDELAY_ID) #20;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--event.sv::20 Unsuported token join ^~~~ERROR (8)::PARSE_ERROR Parser found (3) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: block_start_finishdescription: block start finish checkshould_fail: 0tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::10 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::11 error in parsing: (syntax error, unexpected vDELAY_ID) #200 a = 'h1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::15 Unsuported token join ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::17 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--block_start_finish.sv::22 Unsuported token join ^~~~ERROR (8)::PARSE_ERROR Parser found (4) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: fork_returndescription: illegal return from forkshould_fail: 1tags: 9.3.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.3--fork_return.sv:11: error: Cannot "return" from tasks.1 error(s) during elaboration.
name: block_names_seqdescription: sequential block names checkshould_fail: 0tags: 9.3.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_seq.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_seq.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_seq.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_seq.sv::16 error in parsing: (syntax error, unexpected ':') end: nameERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: block_names_pardescription: parallel block names checkshould_fail: 0tags: 9.3.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv::12 Unsuported token fork: name ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv::12 error in parsing: (syntax error, unexpected ':') fork: namePARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_par.sv::16 Unsuported token join: name ^~~~ERROR (6)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: block_names_seqdescription: sequential block names checkshould_fail: 0tags: 9.3.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.4--block_names_seq.sv']incdirs: []top_module: rc: 0module block_tb; reg a = 0; reg b = 0; reg c = 0; initial begin : name a = 1; b = a; c = b; endendmodule
name: statement_labels_pardescription: parallel block labels checkshould_fail: 0tags: 9.3.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv::12 error in parsing: (syntax error, unexpected ':', expecting voLTE or '=') name: forkPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv::12 Unsuported token name: fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_par.sv::16 Unsuported token join: name ^~~~ERROR (6)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: statement_labels_seqdescription: sequential block labels checkshould_fail: 0tags: 9.3.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_seq.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_seq.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_seq.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.3.5--statement_labels_seq.sv::12 error in parsing: (syntax error, unexpected ':', expecting voLTE or '=') name: beginERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: delay_controldescription: delay controlshould_fail: 0tags: 9.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv']incdirs: []top_module: rc: 0%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv:10: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv:11: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv:12: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv:13: Unsupported: Ignoring delay on this delayed statement.
name: delay_controldescription: delay controlshould_fail: 0tags: 9.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.1--delay_control.sv::10 error in parsing: (syntax error, unexpected vDELAY_ID) #10 a = 'h1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: event_control_negedgedescription: event controlshould_fail: 0tags: 9.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_negedge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_negedge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_negedge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_control_posedgedescription: event controlshould_fail: 0tags: 9.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_posedge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_posedge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_posedge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_control_edgedescription: event controlshould_fail: 0tags: 9.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_edge.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_edge.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_edge.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2--event_control_edge.sv::10 Unsuported token always @(edge clk) a = ~a; ^~~~
name: event_comma_opdescription: event comma operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv' to AST representation.Generating RTLIL representation for module `\block_tb'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv:13 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: event_or_opdescription: event or operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv' to AST representation.Generating RTLIL representation for module `\block_tb'.Note: Assuming pure combinatorial block at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv:13 incompliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommendinguse of @* instead of @(...) for better match of synthesis and simulation.Successfully finished Verilog frontend.
name: event_comma_opdescription: event comma operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_or_opdescription: event or operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_comma_opdescription: event comma operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv:14: error: out is not a valid l-value in block_tb./home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv:12: : out is declared here as wire.Elaboration failed
name: event_or_opdescription: event or operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv:14: error: out is not a valid l-value in block_tb./home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv:12: : out is declared here as wire.Elaboration failed
name: event_comma_opdescription: event comma operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_comma_op.sv']incdirs: []top_module: rc: 0module block_tb; wire a = 0; wire b = 0; wire c = 0; wire d = 0; wire out = 0; always @(a or b or c or d) out = ((a | b) & (c | d));endmodule
name: event_or_opdescription: event or operatorshould_fail: 0tags: 9.4.2.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.1--event_or_op.sv']incdirs: []top_module: rc: 0module block_tb; wire a = 0; wire b = 0; wire c = 0; wire d = 0; wire out = 0; always @(a or b or c or d) out = ((a | b) & (c | d));endmodule
name: event_implicitdescription: event implicit listshould_fail: 0tags: 9.4.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv:13:9: error: language feature not yet supported always @(*) ^~~~
name: event_implicitdescription: event implicit listshould_fail: 0tags: 9.4.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_implicitdescription: event implicit listshould_fail: 0tags: 9.4.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv:14: error: out is not a valid l-value in block_tb./home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv:12: : out is declared here as wire.Elaboration failed
name: event_implicitdescription: event implicit listshould_fail: 0tags: 9.4.2.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.2--event_implicit.sv']incdirs: []top_module: rc: 0module block_tb; wire a = 0; wire b = 0; wire c = 0; wire d = 0; wire out = 0; always @(*) out = ((a | b) & (c | d));endmodule
name: event_conditionaldescription: event conditionalshould_fail: 0tags: 9.4.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv:12:19: error: language feature not yet supported always @(posedge clk iff en == 1) ^~~~~~~~~~~~~~~
name: event_conditionaldescription: event conditionalshould_fail: 0tags: 9.4.2.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.3--event_conditional.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting vOR or ')' or ',') always @(posedge clk iff en == 1)
name: event_sequencedescription: sequence event testshould_fail: 0tags: 9.4.2.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:14: Unsupported: SystemVerilog 2005 reserved word not implemented: sequence%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:14: syntax error, unexpected ';', expecting IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: endsequence%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:19: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:21: syntax error, unexpected '@'%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:26: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:27: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:29: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:30: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:32: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:33: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv:35: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Exiting due to 6 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.2.4--event_sequence.sv
name: event_sequencedescription: event sequenceshould_fail: 0tags: 9.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv']incdirs: []top_module: rc: 10%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv:17: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv:17: syntax error, unexpected '#'%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv
name: event_sequencedescription: event sequenceshould_fail: 0tags: 9.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv::13 error in parsing: (syntax error, unexpected vDELAY_ID) #10 enable = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.3--event_sequence_controls.sv::17 Unsuported token wait (enable) #10 a = b; ^~~~ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_nonblocking_assignment_delaydescription: event non blk assignment delayshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv']incdirs: []top_module: rc: 0%Warning-INITIALDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv:12: Delayed assignments (<=) in initial or final block; suggest blocking assignments (=).%Warning-INITIALDLY: Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message.
name: event_nonblocking_assignment_repeatdescription: event non blk assignment repeatshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv::12 error in parsing: (syntax error, unexpected '=', expecting '(') int i = 3;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv::15 Unsuported token a = repeat(i) @(posedge clk) b; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int.sv::15 error in parsing: (syntax error, unexpected '@', expecting ';') a = repeat(i) @(posedge clk) b;ERROR (6)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_nonblocking_assignment_repeatdescription: event non blk assignment repeatshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv::12 error in parsing: (syntax error, unexpected '=', expecting '(') int i = -3;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv::15 Unsuported token a = repeat(i) @(posedge clk) b; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_int_neg.sv::15 error in parsing: (syntax error, unexpected '@', expecting ';') a = repeat(i) @(posedge clk) b;ERROR (6)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_nonblocking_assignment_delaydescription: event non blk assignment delayshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_delay.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: event_nonblocking_assignment_repeatdescription: event non blk assignment repeatshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv::13 Unsuported token a = repeat(-3) @(posedge clk) b; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat_neg.sv::13 error in parsing: (syntax error, unexpected '@', expecting ';') a = repeat(-3) @(posedge clk) b;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_nonblocking_assignment_repeatdescription: event non blk assignment repeatshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv::13 Unsuported token a = repeat(3) @(posedge clk) b; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_repeat.sv::13 error in parsing: (syntax error, unexpected '@', expecting ';') a = repeat(3) @(posedge clk) b;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: event_nonblocking_assignment_eventdescription: event non blk assignment eventshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_nonblocking_assignment_event.sv::13 error in parsing: (syntax error, unexpected '@') a = @(posedge clk) b;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: event_blocking_assignment_delaydescription: event blk assignment delayshould_fail: 0tags: 9.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_blocking_assignment_delay.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_blocking_assignment_delay.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.4.5--event_blocking_assignment_delay.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: wait_forkdescription: wait fork testshould_fail: 0tags: 9.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:11: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:14: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:15: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:18: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:19: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:20: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:23: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv:23: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.1--wait_fork.sv
name: disable_otherdescription: disable other taskshould_fail: 0tags: 9.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:11: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:14: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:16: syntax error, unexpected '#'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:17: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Exiting due to 3 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv
name: disable_otherdescription: disable other taskshould_fail: 0tags: 9.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv:12: syntax error, unexpected TOK_BEGIN
name: disabledescription: disable blockshould_fail: 0tags: 9.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable.sv::12 Unsuported token disable block; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable.sv::12 error in parsing: (syntax error, unexpected ';', expecting voLTE or '=') disable block;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: disable_otherdescription: disable other taskshould_fail: 0tags: 9.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv::11 Unsuported token initial fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv::13 error in parsing: (syntax error, unexpected vDELAY_ID) #10 a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv::16 Unsuported token #15 disable block; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.2--disable_other.sv::17 Unsuported token join ^~~~
name: disable_forkdescription: disable forkshould_fail: 0tags: 9.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:14: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:15: Unsupported: Ignoring delay on this delayed statement.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:16: Unsupported: SystemVerilog 2005 reserved word not implemented: join_any%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:17: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv:17: syntax error, unexpected ';', expecting IDENTIFIER or PACKAGE-IDENTIFIER or TYPE-IDENTIFIER%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.6.3--disable_fork.sv
name: process_controldescription: process controlshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:9:3: error: use of undeclared identifier 'process' process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:9:19: error: language feature not yet supported process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:11:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:13:23: error: use of undeclared identifier 'j' automatic int k = j; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:15:15: error: unknown class or package 'process' job[k] = process::self(); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:21:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:24:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:29:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~
name: process_cls_awaitdescription: process class await methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:9:3: error: use of undeclared identifier 'process' process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:9:19: error: language feature not yet supported process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:11:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:13:23: error: use of undeclared identifier 'j' automatic int k = j; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:15:15: error: unknown class or package 'process' job[k] = process::self(); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:20:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~
name: process_cls_selfdescription: process class self methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:9:3: error: use of undeclared identifier 'process' process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:9:19: error: language feature not yet supported process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:11:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:13:23: error: use of undeclared identifier 'j' automatic int k = j; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:15:15: error: unknown class or package 'process' job[k] = process::self(); ^~~~~~~
name: process_cls_killdescription: process class kill methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:9:3: error: use of undeclared identifier 'process' process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:9:19: error: language feature not yet supported process job[] = new [N]; ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:11:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:13:23: error: use of undeclared identifier 'j' automatic int k = j; ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:15:15: error: unknown class or package 'process' job[k] = process::self(); ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:20:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:25:3: error: language feature not yet supported foreach(job[i]) ^~~~~~~~~~~~~~~
name: process_controldescription: process controlshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv']incdirs: []top_module: rc: 0
name: process_cls_awaitdescription: process class await methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv']incdirs: []top_module: rc: 0
name: process_cls_selfdescription: process class self methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv']incdirs: []top_module: rc: 0
name: process_cls_killdescription: process class kill methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv']incdirs: []top_module: rc: 0
name: process_controldescription: process controlshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:9: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:13: syntax error, unexpected automatic%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:15: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:15: Perhaps 'process' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:22: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:22: Unsupported: SystemVerilog 2005 reserved word not implemented: null%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:22: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:30: syntax error, unexpected ::%Error: Exiting due to 11 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv
name: process_cls_awaitdescription: process class await methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:9: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:13: syntax error, unexpected automatic%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:15: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:15: Perhaps 'process' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:21: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: null%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:21: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Error: Exiting due to 10 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv
name: process_cls_selfdescription: process class self methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:9: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:13: syntax error, unexpected automatic%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:15: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:15: Perhaps 'process' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: Exiting due to 7 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv
name: process_cls_killdescription: process class kill methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:9: syntax error, unexpected IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: new%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:12: Unsupported: Verilog 1995 reserved word not implemented: fork%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:13: syntax error, unexpected automatic%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:15: syntax error, unexpected ::, expecting ';'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:15: Perhaps 'process' is a package which needs to be predeclared? (IEEE 2012 26.3)%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: join_none%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:21: Unsupported: Verilog 1995 reserved word not implemented: wait%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:21: Unsupported: SystemVerilog 2005 reserved word not implemented: null%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:21: syntax error, unexpected ')', expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:26: syntax error, unexpected ::%Error: Exiting due to 11 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv
name: process_controldescription: process controlshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: process_cls_awaitdescription: process class await methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: process_cls_selfdescription: process class self methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: process_cls_killdescription: process class kill methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: process_controldescription: process controlshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task automatic test (int N);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(') process job[] = new [N];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::18 error in parsing: (syntax error, unexpected vEND) endPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_suspend_resume.sv::22 Unsuported token wait(job[i] != null); ^~~~ERROR (8)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: process_cls_awaitdescription: process class await methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task automatic test (int N);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(') process job[] = new [N];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::17 error in parsing: (syntax error, unexpected vEND) endPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_await.sv::21 Unsuported token wait(job[i] != null); ^~~~ERROR (8)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: process_cls_selfdescription: process class self methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task automatic test (int N);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(') process job[] = new [N];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_self.sv::17 error in parsing: (syntax error, unexpected vEND) endERROR (7)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: process_cls_killdescription: process class kill methodshould_fail: 0tags: 9.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ')' or ',') task automatic test (int N);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::9 error in parsing: (syntax error, unexpected '[', expecting '(') process job[] = new [N];PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::12 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::17 error in parsing: (syntax error, unexpected vEND) endPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-9/9.7--process_cls_kill.sv::21 Unsuported token wait(job[i] != null); ^~~~ERROR (8)::PARSE_ERROR Parser found (2) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: unary_op_not_logdescription: ! operator testshould_fail: 0tags: 11.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv:11: Logical Operator LOGNOT expects 1 bit on the LHS, but LHS's VARREF 'b' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGNOT generates 1 bits.
name: unary_op_not_logdescription: ! operator testshould_fail: 0tags: 11.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_not_log.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_plusdescription: + operator testshould_fail: 0tags: 11.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_plus.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_plus.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_plus.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_plus.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_plus.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_minusdescription: - operator testshould_fail: 0tags: 11.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_minus.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_minus.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_minus.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_minus.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.3--unary_op_minus.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: expr_short_circuitdescription: expression short circuiting testshould_fail: 0tags: 11.3.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv:9: syntax error, unexpected '=', expecting '(' or '['
name: expr_short_circuitdescription: expression short circuiting testshould_fail: 0tags: 11.3.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::12 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';')function int fun1();PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::14 error in parsing: (syntax error, unexpected vNUMBER, expecting vSYMBOL_ID or '#') return 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv::19 error in parsing: (syntax error, unexpected vNUMBER, expecting vSYMBOL_ID or '#') return 2;ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: expr_short_circuitdescription: expression short circuiting testshould_fail: 0tags: 11.3.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.5--expr_short_circuit.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 1; reg signed [31:0] b; function signed [31:0] fun1; input _sv2v_unused; begin $display("1"); fun1 = 1; end endfunction function signed [31:0] fun2; input _sv2v_unused; begin $display("2"); fun2 = 2; end endfunction initial begin b = ((a > 0) ? fun1(0) : fun2(0)); endendmodule
name: assign_in_expr_invdescription: invalid assignment in expression testshould_fail: 1tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv:14:8: error: expression is not assignable a = b = c = 5; ~~~~~ ^
name: assign_in_exprdescription: assignment in expression testshould_fail: 0tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv:14: syntax error, unexpected '='%Error: Exiting due to 1 error(s)%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv
name: assign_in_expr_invdescription: invalid assignment in expression testshould_fail: 1tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv:9: syntax error, unexpected ';', expecting '(' or '['
name: assign_in_exprdescription: assignment in expression testshould_fail: 0tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv:9: syntax error, unexpected ';', expecting '(' or '['
name: assign_in_expr_invdescription: invalid assignment in expression testshould_fail: 1tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv::14 error in parsing: (syntax error, unexpected '=', expecting ';') a = b = c = 5; ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: assign_in_exprdescription: assignment in expression testshould_fail: 0tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr.sv::14 error in parsing: (syntax error, unexpected '=') a = (b = (c = 5)); ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: assign_in_expr_invdescription: invalid assignment in expression testshould_fail: 1tags: 11.3.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv']incdirs: []top_module: rc: 2/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.3.6--assign_in_expr_inv.sv:14: Syntax in assignment statement l-value.
name: or_assignmentdescription: |= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv::11 error in parsing: (syntax error, unexpected '|', expecting voLTE or '=') a |= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: mul_assignmentdescription: *= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv::11 error in parsing: (syntax error, unexpected '*', expecting voLTE or '=') a *= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: xor_assignmentdescription: ^= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv::11 error in parsing: (syntax error, unexpected '^', expecting voLTE or '=') a ^= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: arith_shl_assignmentdescription: <<<= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv::11 error in parsing: (syntax error, unexpected voSLEFT, expecting voLTE or '=') a <<<= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: normal_assignmentdescription: = assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: plus_assignmentdescription: += assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv::11 error in parsing: (syntax error, unexpected '+', expecting voLTE or '=') a += b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: and_assignmentdescription: &= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv::11 error in parsing: (syntax error, unexpected '&', expecting voLTE or '=') a &= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: div_assignmentdescription: /= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv::11 error in parsing: (syntax error, unexpected '/', expecting voLTE or '=') a /= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: arith_shr_assignmentdescription: >>>= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv::11 error in parsing: (syntax error, unexpected voASRIGHT, expecting voLTE or '=') a >>>= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: mod_assignmentdescription: %= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv::11 error in parsing: (syntax error, unexpected '%', expecting voLTE or '=') a %= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: log_shl_assignmentdescription: <<= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv::11 error in parsing: (syntax error, unexpected voSLEFT, expecting voLTE or '=') a <<= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: log_shr_assignmentdescription: >>= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv::11 error in parsing: (syntax error, unexpected voSRIGHT, expecting voLTE or '=') a >>= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: minus_assignmentdescription: -= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv::11 error in parsing: (syntax error, unexpected '-', expecting voLTE or '=') a -= b;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: or_assignmentdescription: |= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--or_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a | b); endendmodule
name: mul_assignmentdescription: *= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mul_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a * b); endendmodule
name: xor_assignmentdescription: ^= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--xor_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a ^ b); endendmodule
name: arith_shl_assignmentdescription: <<<= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shl_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a <<< b); endendmodule
name: normal_assignmentdescription: = assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--normal_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = b; endendmodule
name: plus_assignmentdescription: += assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--plus_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a + b); endendmodule
name: and_assignmentdescription: &= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--and_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a & b); endendmodule
name: div_assignmentdescription: /= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--div_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a / b); endendmodule
name: arith_shr_assignmentdescription: >>>= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--arith_shr_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a >>> b); endendmodule
name: mod_assignmentdescription: %= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--mod_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a % b); endendmodule
name: log_shl_assignmentdescription: <<= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shl_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a << b); endendmodule
name: log_shr_assignmentdescription: >>= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--log_shr_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a >> b); endendmodule
name: minus_assignmentdescription: -= assignment testshould_fail: 0tags: 11.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/assignment_op/11.4.1--minus_assignment.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (a - b); endendmodule
name: unary_op_incdescription: ++ operator testshould_fail: 0tags: 11.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_inc.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_inc.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_inc.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_inc.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_inc.sv::12 error in parsing: (syntax error, unexpected '+', expecting voLTE or '=') a++;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unary_op_decdescription: -- operator testshould_fail: 0tags: 11.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_dec.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_dec.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_dec.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_dec.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.2--unary_op_dec.sv::12 error in parsing: (syntax error, unexpected '-', expecting voLTE or '=') a--;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: binary_op_minusdescription: - operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_minus.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a - b); endendmodule
name: binary_op_divdescription: / operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_div.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a / b); endendmodule
name: binary_op_plusdescription: + operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_plus.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a + b); endendmodule
name: binary_op_powdescription: ** operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_pow.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a ** b); endendmodule
name: binary_op_muldescription: * operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_mul.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a * b); endendmodule
name: binary_op_moddescription: % operator testshould_fail: 0tags: 11.4.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.3--binary_op_mod.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a % b); endendmodule
name: binary_op_gedescription: >= operator testshould_fail: 0tags: 11.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.4--binary_op_ge.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a >= b); endendmodule
name: binary_op_gtdescription: > operator testshould_fail: 0tags: 11.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.4--binary_op_gt.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a > b); endendmodule
name: binary_op_ledescription: <= operator testshould_fail: 0tags: 11.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.4--binary_op_le.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a <= b); endendmodule
name: binary_op_ltdescription: < operator testshould_fail: 0tags: 11.4.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.4--binary_op_lt.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a < b); endendmodule
name: binary_op_case_eqdescription: === operator testshould_fail: 0tags: 11.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.5--binary_op_case_eq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a === b); endendmodule
name: binary_op_case_neqdescription: !== operator testshould_fail: 0tags: 11.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.5--binary_op_case_neq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a !== b); endendmodule
name: binary_op_log_eqdescription: == operator testshould_fail: 0tags: 11.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.5--binary_op_log_eq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a == b); endendmodule
name: binary_op_log_neqdescription: != operator testshould_fail: 0tags: 11.4.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.5--binary_op_log_neq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a != b); endendmodule
name: binary_op_wild_eqdescription: ==? operator testshould_fail: 0tags: 11.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv::12 error in parsing: (syntax error, unexpected '?') c = a ==? b;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: binary_op_wild_neqdescription: !=? operator testshould_fail: 0tags: 11.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv::12 error in parsing: (syntax error, unexpected '?') c = a !=? b;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: binary_op_wild_eqdescription: ==? operator testshould_fail: 0tags: 11.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_eq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a ==? b); endendmodule
name: binary_op_wild_neqdescription: !=? operator testshould_fail: 0tags: 11.4.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.6--binary_op_wild_neq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a !=? b); endendmodule
name: binary_op_log_impdescription: -> operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv:12: Logical Operator LOGIF expects 1 bit on the LHS, but LHS's VARREF 'a' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv:12: Logical Operator LOGIF expects 1 bit on the RHS, but RHS's VARREF 'b' generates 32 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGIF generates 1 bits.
name: binary_op_log_ordescription: || operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv:12: Logical Operator LOGOR expects 1 bit on the LHS, but LHS's VARREF 'a' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv:12: Logical Operator LOGOR expects 1 bit on the RHS, but RHS's VARREF 'b' generates 32 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGOR generates 1 bits.
name: binary_op_log_anddescription: && operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv:12: Logical Operator LOGAND expects 1 bit on the LHS, but LHS's VARREF 'a' generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv:12: Logical Operator LOGAND expects 1 bit on the RHS, but RHS's VARREF 'b' generates 32 bits.%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv:12: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGAND generates 1 bits.
name: binary_op_log_impdescription: -> operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv::12 error in parsing: (syntax error, unexpected '>') c = a -> b;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: binary_op_log_ordescription: || operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: binary_op_log_eqdescription: <-> operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv::12 error in parsing: (syntax error, unexpected '>') c = a <-> b;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: binary_op_log_anddescription: && operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: binary_op_log_impdescription: -> operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_imp.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = ((! a) || b); endendmodule
name: binary_op_log_ordescription: || operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_or.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a || b); endendmodule
name: binary_op_log_eqdescription: <-> operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_eq.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = ((! a) == (! b)); endendmodule
name: binary_op_log_anddescription: && operator testshould_fail: 0tags: 11.4.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.7--binary_op_log_and.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a && b); endendmodule
name: binary_op_bit_xordescription: ^ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: binary_op_bit_xnordescription: ~^ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: binary_op_bit_ordescription: | operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: binary_op_bit_anddescription: & operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int c;
name: unary_op_not_bitdescription: ~ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: binary_op_bit_xordescription: ^ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xor.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a ^ b); endendmodule
name: binary_op_bit_xnordescription: ~^ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_xnor.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a ~^ b); endendmodule
name: binary_op_bit_ordescription: | operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_or.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a | b); endendmodule
name: binary_op_bit_anddescription: & operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.8--binary_op_bit_and.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a & b); endendmodule
name: unary_op_not_bitdescription: ~ operator testshould_fail: 0tags: 11.4.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.8--unary_op_not_bit.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a = 12; wire signed [31:0] b = 5; initial begin a = (~ b); endendmodule
name: unary_op_xordescription: ^ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REDXOR generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_nanddescription: ~& operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGNOT generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_xnor_1description: ~^ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REDXNOR generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_anddescription: & operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REDAND generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_xnor_2description: ^~ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REDXNOR generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_ordescription: | operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's REDOR generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_nordescription: ~| operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv:11: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's LOGNOT generates 1 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unary_op_xordescription: ^ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xor.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_nanddescription: ~& operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nand.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_xnor_1description: ~^ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_1.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_anddescription: & operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_and.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_xnor_2description: ^~ operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_xnor_2.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_ordescription: | operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_or.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: unary_op_nordescription: ~| operator testshould_fail: 0tags: 11.4.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/unary_op/11.4.9--unary_op_nor.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 5;
name: binary_op_log_shldescription: << operator testshould_fail: 0tags: 11.4.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.10--binary_op_log_shl.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a << b); endendmodule
name: binary_op_arith_shrdescription: >>> operator testshould_fail: 0tags: 11.4.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.10--binary_op_arith_shr.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a >>> b); endendmodule
name: binary_op_log_shrdescription: >> operator testshould_fail: 0tags: 11.4.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.10--binary_op_log_shr.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a >> b); endendmodule
name: binary_op_arith_shldescription: <<< operator testshould_fail: 0tags: 11.4.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/binary_op/11.4.10--binary_op_arith_shl.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = (a <<< b); endendmodule
name: cond_opdescription: ?: operator testshould_fail: 0tags: 11.4.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.11--cond_op.sv']incdirs: []top_module: rc: 0module top; wire signed [31:0] a = 12; wire signed [31:0] b = 5; reg signed [31:0] c; initial begin c = ((a > b) ? 11 : 13); endendmodule
name: concat_opdescription: concatenation operator testshould_fail: 0tags: 11.4.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12--concat_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12--concat_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12--concat_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12--concat_op.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [15:0] a;
name: repl_opdescription: replication operator testshould_fail: 0tags: 11.4.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--repl_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--repl_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--repl_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--repl_op.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [15:0] a;
name: nested_repl_opdescription: nested replication operator testshould_fail: 0tags: 11.4.12.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--nested_repl_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--nested_repl_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--nested_repl_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.1--nested_repl_op.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [15:0] a;
name: string_concat_opdescription: string concatenation operator testshould_fail: 0tags: 11.4.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_concat_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_concat_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_concat_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_concat_op.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')string str;
name: string_repl_opdescription: string replication operator testshould_fail: 0tags: 11.4.12.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_repl_op.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_repl_op.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_repl_op.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.12.2--string_repl_op.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')string str;
name: set_memberdescription: inside operator testshould_fail: 0tags: 11.4.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')int a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(')int c = 5;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::12 error in parsing: (syntax error, unexpected '=', expecting '(')int d = 7;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = b inside {c, d};ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: set_memberdescription: inside operator testshould_fail: 0tags: 11.4.13files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.13--set_member.sv']incdirs: []top_module: rc: 0module top; reg signed [31:0] a; wire signed [31:0] b = 12; wire signed [31:0] c = 5; wire signed [31:0] d = 7; initial begin a = ((b == c) || (b == d)); endendmodule
name: stream_concatdescription: stream concatenation testshould_fail: 0tags: 11.4.14.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv:14:6: error: language feature not yet supported c = {>> byte {a, b}}; ^~~~~~~~~~~~~~~~
name: stream_concatdescription: stream concatenation testshould_fail: 0tags: 11.4.14.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = {"A", "B", "C", "D"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(')int b = {"E", "F", "G", "H"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.1--stream_concat.sv::14 error in parsing: (syntax error, unexpected voSRIGHT) c = {>> byte {a, b}};ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: reorder_streamdescription: stream reordering testshould_fail: 0tags: 11.4.14.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = {"A", "B", "C", "D"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv::10 error in parsing: (syntax error, unexpected ';', expecting '(')int b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.2--reorder_stream.sv::13 error in parsing: (syntax error, unexpected voSLEFT) b = { << byte {a}};ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpack_stream_paddescription: padded stream unpack testshould_fail: 0tags: 11.4.14.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(')int c = 3;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_pad.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') bit [127:0] d = {<<{a, b, c}};ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpack_streamdescription: stream unpack testshould_fail: 0tags: 11.4.14.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(')int c = 3;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') bit [95:0] d = {<<{a, b, c}};ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unpack_stream_invdescription: invalid stream unpack testshould_fail: 1tags: 11.4.14.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv::9 error in parsing: (syntax error, unexpected '=', expecting '(')int a = 1;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv::10 error in parsing: (syntax error, unexpected '=', expecting '(')int b = 2;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv::11 error in parsing: (syntax error, unexpected '=', expecting '(')int c = 3;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.4.14.3--unpack_stream_inv.sv::14 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') int d = {<<{a, b, c}};ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: idx_neg_part_selectdescription: indexed negative part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: non_idx_part_selectdescription: non-indexed part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: idx_pos_part_selectdescription: indexed positive part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: idx_pos_part_selectdescription: indexed positive part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: idx_neg_part_selectdescription: indexed negative part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_neg_part_select.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [15:0] a;
name: non_idx_part_selectdescription: non-indexed part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--non_idx_part_select.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [15:0] a;
name: idx_pos_part_selectdescription: indexed positive part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [15:0] a;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_select.sv::9 error in parsing: (syntax error, unexpected ';', expecting '(')logic b;
name: idx_pos_part_selectdescription: indexed positive part-select bit testshould_fail: 0tags: 11.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.1--idx_pos_part_select.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [15:0] a;
name: array_addressingdescription: array addressing testshould_fail: 0tags: 11.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--array_addressing.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--array_addressing.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--array_addressing.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--array_addressing.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [7:0] mem [0:1023];
name: array_addressingdescription: array addressing testshould_fail: 0tags: 11.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--multi_dim_array_addressing.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--multi_dim_array_addressing.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--multi_dim_array_addressing.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.5.2--multi_dim_array_addressing.sv::8 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [7:0] mem [0:1023][0:3];
name: signed_funcdescription: $signed() testshould_fail: 0tags: 11.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv:12: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's SIGNED generates 4 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: unsigned_funcdescription: $unsigned() testshould_fail: 0tags: 11.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv']incdirs: []top_module: rc: 0%Warning-WIDTH: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv:12: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's UNSIGNED generates 32 bits.%Warning-WIDTH: Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
name: signed_funcdescription: $signed() testshould_fail: 0tags: 11.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--signed_func.sv::9 error in parsing: (syntax error, unexpected vSIGNED, expecting vSYMBOL_ID or '#')logic signed [7:0] a;
name: unsigned_funcdescription: $unsigned() testshould_fail: 0tags: 11.7files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.7--unsigned_func.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [7:0] a;
name: tagged_union_member_access_invdescription: invalid tagged union member access testshould_fail: 1tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:9:9: error: language feature not yet supportedtypedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:19:6: error: language feature not yet supported a = tagged Invalid; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:20:6: error: language feature not yet supported b = tagged Valid(42); ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:20:18: error: expected ';' b = tagged Valid(42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:20:18: error: expected statement b = tagged Valid(42); ^
name: tagged_union_member_accessdescription: tagged union member access testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:9:9: error: language feature not yet supportedtypedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:19:6: error: language feature not yet supported a = tagged Invalid; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:20:6: error: language feature not yet supported b = tagged Valid(42); ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:20:18: error: expected ';' b = tagged Valid(42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:20:18: error: expected statement b = tagged Valid(42); ^
name: tagged_uniondescription: tagged union testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:9:9: error: language feature not yet supportedtypedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:17:6: error: language feature not yet supported a = tagged Invalid; ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:18:6: error: language feature not yet supported b = tagged Valid(42); ^~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:18:18: error: expected ';' b = tagged Valid(42); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:18:18: error: expected statement b = tagged Valid(42); ^
name: tagged_union_member_access_invdescription: invalid tagged union member access testshould_fail: 1tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv']incdirs: []top_module: rc: 0
name: tagged_union_member_accessdescription: tagged union member access testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv']incdirs: []top_module: rc: 0
name: tagged_union_member_access_invdescription: invalid tagged union member access testshould_fail: 1tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:10: syntax error, unexpected void, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:12: syntax error, unexpected '}'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:7: ../V3ParseSym.h:112: Symbols suggest ending UNIONDTYPE but parser thinks ending MODULE 'top'%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv
name: tagged_union_member_accessdescription: tagged union member access testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:10: syntax error, unexpected void, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:12: syntax error, unexpected '}'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:19: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:20: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:7: ../V3ParseSym.h:112: Symbols suggest ending UNIONDTYPE but parser thinks ending MODULE 'top'%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv
name: tagged_uniondescription: tagged union testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:10: syntax error, unexpected void, expecting TYPE-IDENTIFIER%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:12: syntax error, unexpected '}'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:17: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:18: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Internal Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:7: ../V3ParseSym.h:112: Symbols suggest ending UNIONDTYPE but parser thinks ending MODULE 'top'%Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv
name: tagged_union_member_access_invdescription: invalid tagged union member access testshould_fail: 1tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: tagged_union_member_accessdescription: tagged union member access testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: tagged_uniondescription: tagged union testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: tagged_union_member_access_invdescription: invalid tagged union member access testshould_fail: 1tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(') int Valid;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::14 error in parsing: (syntax error, unexpected ',', expecting '(')u_int a, b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::16 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access_inv.sv::19 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = tagged Invalid;ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: tagged_union_member_accessdescription: tagged union member access testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(') int Valid;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::14 error in parsing: (syntax error, unexpected ',', expecting '(')u_int a, b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::16 error in parsing: (syntax error, unexpected ';', expecting '(')int c;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union_member_access.sv::19 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = tagged Invalid;ERROR (8)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: tagged_uniondescription: tagged union testshould_fail: 0tags: 11.9files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(')typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv::11 error in parsing: (syntax error, unexpected ';', expecting '(') int Valid;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv::14 error in parsing: (syntax error, unexpected ',', expecting '(')u_int a, b;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.9--tagged_union.sv::17 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ';') a = tagged Invalid;ERROR (7)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv' to AST representation.Generating RTLIL representation for module `\top'.Successfully finished Verilog frontend.
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [8*14:1] a;
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0
name: string_bit_arraydescription: string stored in bit array testshould_fail: 0tags: 11.10files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10--string_bit_array.sv']incdirs: []top_module: rc: 0module top; reg [112:1] a; initial begin a = "Test"; endendmodule
name: string_concatdescription: string concatenation testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Failed to evaluate system task `$display' with non-constant 1st argument at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv:15.
name: string_comparedescription: string comparison testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Failed to evaluate system task `$display' with non-constant 1st argument at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv:15.
name: string_copydescription: string copy testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Failed to evaluate system task `$display' with non-constant 1st argument at /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv:15.
name: string_concatdescription: string concatenation testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_concat.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [8*14:1] a;
name: string_comparedescription: string comparison testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_compare.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [8*14:1] a;
name: string_copydescription: string copy testshould_fail: 0tags: 11.10.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.1--string_copy.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [8*14:1] a;
name: empty_stringdescription: empty string testshould_fail: 0tags: 11.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv:13: Unsupported or unknown PLI call: $assert%Error: Exiting due to 1 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv
name: empty_stringdescription: empty string testshould_fail: 0tags: 11.10.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.10.3--empty_string.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')bit [8*14:1] a;
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv:10:4: error: language feature not yet supported #(100:200:300) $display("Done"); ^~~~~~~~~~~
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: 0
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: 0%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv:10: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv' to AST representation.Generating RTLIL representation for module `\top'.DoneSuccessfully finished Verilog frontend.
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv::10 error in parsing: (syntax error, unexpected ':', expecting ')' or ',') #(100:200:300) $display("Done");ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: min_max_avg_delaydescription: minimum, typical and maximum delay expressions testshould_fail: 0tags: 11.11files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv']incdirs: []top_module: rc: 0/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.11--min_max_avg_delay.sv:10: warning: choosing typ expression.
name: let_constructdescription: let construct testshould_fail: 0tags: 11.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv:14: Unsupported: SystemVerilog 2009 reserved word not implemented: let%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv:14: syntax error, unexpected '(', expecting IDENTIFIER%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv
name: let_constructdescription: let construct testshould_fail: 0tags: 11.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv:14: syntax error, unexpected '=', expecting ',' or ';'
name: let_constructdescription: let construct testshould_fail: 0tags: 11.12files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv::9 error in parsing: (syntax error, unexpected '[', expecting vSYMBOL_ID or '#')logic [3:0] a = 12;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv::12 error in parsing: (syntax error, unexpected ';', expecting '(')logic d;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-11/11.12--let_construct.sv::14 error in parsing: (syntax error, unexpected '=', expecting ';' or ',')let op(x, y, z) = |((x | y) & z);
name: ifdescription: A module testing if statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv' to AST representation.Generating RTLIL representation for module `\if_tb'.Successfully finished Verilog frontend.
name: ifdescription: A module testing if-else statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv' to AST representation.Generating RTLIL representation for module `\if_tb'.Successfully finished Verilog frontend.
name: ifdescription: A module testing if statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: ifdescription: A module testing if-else statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: ifdescription: A module testing if statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: ifdescription: A module testing if-else statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: ifdescription: A module testing if statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if.sv']incdirs: []top_module: rc: 0module if_tb; wire a = 0; reg b = 0; always begin if (a) b = 1; endendmodule
name: ifdescription: A module testing if-else statementshould_fail: 0tags: 12.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4--if_else.sv']incdirs: []top_module: rc: 0module if_tb; wire a = 0; reg b = 0; always begin if (a) b = 1; else b = 0; endendmodule
name: if_else_ifdescription: A module testing if-else-if statementshould_fail: 0tags: 12.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv' to AST representation.Generating RTLIL representation for module `\if_tb'.Successfully finished Verilog frontend.
name: if_else_ifdescription: A module testing if-else-if statementshould_fail: 0tags: 12.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }
name: if_else_ifdescription: A module testing if-else-if statementshould_fail: 0tags: 12.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv:12: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv:12: : A runtime infinite loop will occur.Elaboration failed
name: if_else_ifdescription: A module testing if-else-if statementshould_fail: 0tags: 12.4.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.1--if_else_if.sv']incdirs: []top_module: rc: 0module if_tb; wire a = 0; reg b = 0; wire c = 0; reg d = 0; always begin if (a) b = 1; else if (c) d = 1; else b = 0; endendmodule
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv:11: syntax error, unexpected TOK_IF
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv:11: syntax error, unexpected TOK_IF
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv:11: syntax error, unexpected TOK_IF
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv::11 error in parsing: (syntax error, unexpected vIF, expecting voLTE or '=') unique if(a == 0) b = 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv::11 error in parsing: (syntax error, unexpected vIF, expecting voLTE or '=') unique0 if(a == 0) b = 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv::11 error in parsing: (syntax error, unexpected vIF, expecting voLTE or '=') priority if(a[0] == 0) b = 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv:11: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv:12: Syntax in assignment statement l-value.
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv:11: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv:12: Syntax in assignment statement l-value.
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv']incdirs: []top_module: rc: 4/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv:11: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv:12: Syntax in assignment statement l-value.
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique_if.sv']incdirs: []top_module: rc: 0module if_tb; wire [3:0] a = 0; reg [1:0] b = 0; always begin if ((a == 0)) b = 1; else if ((a == 1)) b = 2; endendmodule
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--unique0_if.sv']incdirs: []top_module: rc: 0module if_tb; wire [3:0] a = 0; reg [1:0] b = 0; always begin if ((a == 0)) b = 1; else if ((a == 1)) b = 2; endendmodule
name: unique_ifdescription: A module testing unique-if statementshould_fail: 0tags: 12.4.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.4.2--priority_if.sv']incdirs: []top_module: rc: 0module if_tb; wire [3:0] a = 0; reg [1:0] b = 0; always begin if ((a[0] == 0)) b = 1; else if ((a[1] == 0)) b = 2; endendmodule
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 0
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 0
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 0
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv' to AST representation.Generating RTLIL representation for module `\case_tb'.Successfully finished Verilog frontend.
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv::15 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ':') default b = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: casedescription: A module testing case statementshould_fail: 0tags: 12.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5--case.sv']incdirs: []top_module: rc: 0module case_tb; wire [3:0] a = 0; reg [3:0] b = 0; always begin case (a) 4'h0: b = 12; 4'h3: b = 4; 4'hf: b = 8; default: b = 0; endcase endendmodule
name: casexdescription: A module testing casex statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv']incdirs: []top_module: rc: 0%Warning-CASEX: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv:11: Suggest casez (with ?'s) in place of casex (with X's)%Warning-CASEX: Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message.
name: casezdescription: A module testing casez statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv:8)Generating RTLIL representation for module `\case_tb'.Successfully finished Verilog frontend.
name: casexdescription: A module testing casex statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv' to AST representation.Warning: Yosys has only limited support for tri-state logic at the moment. (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv:8)Generating RTLIL representation for module `\case_tb'.Successfully finished Verilog frontend.
name: casezdescription: A module testing casez statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv::11 Unsuported token casez(a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv::11 error in parsing: (syntax error, unexpected '(') casez(a)ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: casexdescription: A module testing casex statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv::11 Unsuported token casex(a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv::11 error in parsing: (syntax error, unexpected '(') casex(a)ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: casezdescription: A module testing casez statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: casexdescription: A module testing casex statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: casezdescription: A module testing casez statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casez.sv']incdirs: []top_module: rc: 0module case_tb; wire [3:0] a = 4'b1z11; reg [3:0] b = 0; always begin casez (a) 4'b1zzz: b = 1; 4'b01z?: b = 2; 4'b001z: b = 3; 4'b0001: b = 4; default: b = 0; endcase endendmodule
name: casexdescription: A module testing casex statementshould_fail: 0tags: 12.5.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.1--casex.sv']incdirs: []top_module: rc: 0module case_tb; wire [3:0] a = 4'b10zx; reg [3:0] b = 0; always begin casex (a) 4'b1xz?: b = 1; 4'b01xx: b = 2; 4'b001x: b = 3; 4'b0001: b = 4; default: b = 0; endcase endendmodule
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 0
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 0
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 0
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 0-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.Parsing SystemVerilog input from `/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv' to AST representation.Generating RTLIL representation for module `\case_tb'.Successfully finished Verilog frontend.
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv::16 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting ':') default b = 0;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv:10: error: always statement does not have any delay./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv:10: : A runtime infinite loop will occur.Elaboration failed
name: case_constantdescription: A module testing case statement with constant expressionshould_fail: 0tags: 12.5.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.2--case_const.sv']incdirs: []top_module: rc: 0module case_tb; wire [3:0] a = 0; reg [3:0] b = 0; always begin case (1) a[0]: b = 1; a[1]: b = 2; a[2]: b = 3; a[3]: b = 4; default: b = 0; endcase endendmodule
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: 0
name: priority_casexdescription: casex statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv']incdirs: []top_module: rc: 0%Warning-CASEX: /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:11: Suggest casez (with ?'s) in place of casex (with X's)%Warning-CASEX: Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message.
name: unique_casexdescription: casex statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv']incdirs: []top_module: rc: 0%Warning-CASEX: /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:11: Suggest casez (with ?'s) in place of casex (with X's)%Warning-CASEX: Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message.
name: unique0_casexdescription: casex statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv']incdirs: []top_module: rc: 0%Warning-CASEX: /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:11: Suggest casez (with ?'s) in place of casex (with X's)%Warning-CASEX: Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message.
name: priority_casedescription: case statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv']incdirs: []top_module: rc: 0
name: unique0_casedescription: case statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv']incdirs: []top_module: rc: 0
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: 0
name: priority_casexdescription: casex statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:11: syntax error, unexpected TOK_CASEX
name: unique_casexdescription: casex statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:11: syntax error, unexpected TOK_CASEX
name: unique_casezdescription: casez statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:11: syntax error, unexpected TOK_CASEZ
name: unique0_casexdescription: casex statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:11: syntax error, unexpected TOK_CASEX
name: priority_casedescription: case statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:11: syntax error, unexpected TOK_CASE
name: unique0_casedescription: case statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:11: syntax error, unexpected TOK_CASE
name: unique0_casezdescription: casez statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:11: syntax error, unexpected TOK_CASEZ
name: priority_casezdescription: casez statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:11: syntax error, unexpected TOK_CASEZ
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:11: syntax error, unexpected TOK_CASE
name: priority_casexdescription: casex statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv::11 Unsuported token priority casex (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: unique_casexdescription: casex statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv::11 Unsuported token unique casex (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: unique_casezdescription: casez statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv::11 Unsuported token unique casez (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: unique0_casexdescription: casex statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv::11 Unsuported token unique0 casex (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: priority_casedescription: case statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv::11 error in parsing: (syntax error, unexpected vCASE, expecting voLTE or '=') priority case (a)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unique0_casedescription: case statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv::11 error in parsing: (syntax error, unexpected vCASE, expecting voLTE or '=') unique0 case (a)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: unique0_casezdescription: casez statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv::11 Unsuported token unique0 casez (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: priority_casezdescription: casez statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv::11 Unsuported token priority casez (a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv::12 error in parsing: (syntax error, unexpected vNUMBER, expecting ';') 0, 1: b = 1;ERROR (5)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv::11 error in parsing: (syntax error, unexpected vCASE, expecting voLTE or '=') unique case (a)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: priority_casexdescription: casex statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv:15: syntax errorI give up.
name: unique_casexdescription: casex statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv:15: syntax errorI give up.
name: unique_casezdescription: casez statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv:15: syntax errorI give up.
name: unique0_casexdescription: casex statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv:15: syntax errorI give up.
name: priority_casedescription: case statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv:15: syntax errorI give up.
name: unique0_casedescription: case statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv:15: syntax errorI give up.
name: unique0_casezdescription: casez statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv:15: syntax errorI give up.
name: priority_casezdescription: casez statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv:15: syntax errorI give up.
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: 8/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:12: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:14: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:14: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv:15: syntax errorI give up.
name: priority_casexdescription: casex statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casex.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casex (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique_casexdescription: casex statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casex.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casex (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique_casezdescription: casez statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_casez.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casez (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique0_casexdescription: casex statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casex.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casex (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: priority_casedescription: case statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_case.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin case (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique0_casedescription: case statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_case.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin case (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique0_casezdescription: casez statement with unique0should_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique0_casez.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casez (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: priority_casezdescription: casez statement with priorityshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--priority_casez.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin casez (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: unique_casedescription: case statement with uniqueshould_fail: 0tags: 12.5.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/generated/uniquecase/12.5.3--unique_case.sv']incdirs: []top_module: rc: 0module top; wire [3:0] a = 3; reg [3:0] b = 0; initial begin case (a) 0, 1: b = 1; 2: b = 2; 3: b = 3; endcase endendmodule
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:11:11: error: language feature not yet supported case(a) inside ^~~~~~
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 0
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 0
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:12: Syntax error.
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv::12 error in parsing: (syntax error, unexpected vNUMBER) 1, 3: b = 1;ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 5/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:11: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:12: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:13: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:13: Syntax in assignment statement l-value./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:13: error: Incomprehensible case expression.
name: case_setdescription: A module testing case set membershipshould_fail: 0tags: 12.5.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.5.4--case_set.sv:11:25: Parse error: unexpected token 'inside' (KW_inside).
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9:10: error: language feature not yet supported typedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:23:19: error: language feature not yet supported initial case (v) matches ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24:11: error: expected ':' tagged a '{.v, 0} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24:14: error: expected identifier tagged a '{.v, 0} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24:20: error: expected ';' tagged a '{.v, 0} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24:21: error: expected member tagged a '{.v, 0} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:25:3: error: expected member tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:26:3: error: expected member tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:27:3: error: expected member tagged c '{0, .v} : $display("c %d", v); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:28:2: error: expected member endcase ^~~~~~~
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:9:10: error: language feature not yet supported typedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:23:20: error: language feature not yet supported initial casex (v) matches ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24:11: error: expected ':' tagged a '{.v, 4'b00?x} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24:14: error: expected identifier tagged a '{.v, 4'b00?x} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24:26: error: expected ';' tagged a '{.v, 4'b00?x} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24:27: error: expected member tagged a '{.v, 4'b00?x} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:25:3: error: expected member tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:26:3: error: expected member tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:27:3: error: expected member tagged c '{4'h??0x, .v} : $display("c %d", v); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:28:2: error: expected member endcase ^~~~~~~
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:9:10: error: language feature not yet supported typedef union tagged { ^~~~~~~~~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:23:20: error: language feature not yet supported initial casez (v) matches ^~~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24:11: error: expected ':' tagged a '{.v, 4'bzz0?} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24:14: error: expected identifier tagged a '{.v, 4'bzz0?} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24:26: error: expected ';' tagged a '{.v, 4'bzz0?} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24:27: error: expected member tagged a '{.v, 4'bzz0?} : $display("a %d", v); ^../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:25:3: error: expected member tagged a '{.v1, .v2} : $display("a %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:26:3: error: expected member tagged b '{.v1, .v2} : $display("b %d %d", v1, v2); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:27:3: error: expected member tagged c '{4'hz00?, .v} : $display("c %d", v); ^~~~~~../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:28:2: error: expected member endcase ^~~~~~~
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 0
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: 0
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: 0
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24: syntax error, unexpected "'{", expecting ',' or ':'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24: syntax error, unexpected "'{", expecting ',' or ':'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24: syntax error, unexpected "'{", expecting ',' or ':'%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:25: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:27: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: Cannot continue%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::21 error in parsing: (syntax error, unexpected ';', expecting '(') u tmp;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::24 error in parsing: (syntax error, unexpected vSYMBOL_ID) tagged a '{.v, 0} : $display("a %d", v);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::25 error in parsing: (syntax error, unexpected '{', expecting '(') tagged a '{.v1, .v2} : $display("a %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::26 error in parsing: (syntax error, unexpected '{', expecting '(') tagged b '{.v1, .v2} : $display("b %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv::27 error in parsing: (syntax error, unexpected '{', expecting '(') tagged c '{0, .v} : $display("c %d", v);ERROR (9)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::21 error in parsing: (syntax error, unexpected ';', expecting '(') u tmp;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::23 Unsuported token initial casex (v) matches ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::25 error in parsing: (syntax error, unexpected '{', expecting '(') tagged a '{.v1, .v2} : $display("a %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::26 error in parsing: (syntax error, unexpected '{', expecting '(') tagged b '{.v1, .v2} : $display("b %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv::27 error in parsing: (syntax error, unexpected '{', expecting '(') tagged c '{4'h??0x, .v} : $display("c %d", v);ERROR (9)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::21 error in parsing: (syntax error, unexpected ';', expecting '(') u tmp;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::23 Unsuported token initial casez (v) matches ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::25 error in parsing: (syntax error, unexpected '{', expecting '(') tagged a '{.v1, .v2} : $display("a %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::26 error in parsing: (syntax error, unexpected '{', expecting '(') tagged b '{.v1, .v2} : $display("b %d %d", v1, v2);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv::27 error in parsing: (syntax error, unexpected '{', expecting '(') tagged c '{4'hz00?, .v} : $display("c %d", v);ERROR (9)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 18/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9: error: Syntax error in typedef clause./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:13: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:16: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:19: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:19: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:21: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:21: error: Invalid module instantiation/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:23: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:24: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:25: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:25: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:26: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:26: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:27: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:27: error: Incomprehensible case expression.
name: casex_patterndescription: A module testing pattern matching in casex statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv']incdirs: []top_module: rc: 18/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:9: error: Syntax error in typedef clause./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:13: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:16: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:19: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:19: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:21: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:21: error: Invalid module instantiation/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:23: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:24: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:25: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:25: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:26: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:26: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:27: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:27: warning: extra digits given for sized hex constant./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casex_pattern.sv:27: error: Incomprehensible case expression.
name: casez_patterndescription: A module testing pattern matching in casez statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv']incdirs: []top_module: rc: 18/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:9: error: Syntax error in typedef clause./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:13: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:16: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:19: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:19: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:21: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:21: error: Invalid module instantiation/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:23: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:24: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:25: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:25: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:26: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:26: error: Incomprehensible case expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:27: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:27: warning: extra digits given for sized hex constant./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--casez_pattern.sv:27: error: Incomprehensible case expression.
name: case_patterndescription: A module testing pattern matching in case statementsshould_fail: 0tags: 12.6.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.1--case_pattern.sv:9:23: Parse error: unexpected token 'tagged' (KW_tagged).
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 3internal compiler error: Unexpected index
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 0
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:23: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:23: syntax error, unexpected IDENTIFIER%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: -11--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv::21 error in parsing: (syntax error, unexpected ';', expecting '(') u tmp;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv::23 error in parsing: (syntax error, unexpected vSYMBOL_ID) initial if (tmp matches tagged a '{4'b01zx, .v})
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 12/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:9: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:9: error: Syntax error in typedef clause./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:12: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:12: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:13: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:16: sorry: Unpacked structs not supported./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:19: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:19: error: invalid module item./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:21: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:21: error: Invalid module instantiation/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:23: syntax error/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:23: error: Malformed conditional expression.
name: if_patterndescription: A module testing pattern matching in if statementsshould_fail: 0tags: 12.6.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.2--if_pattern.sv:9:23: Parse error: unexpected token 'tagged' (KW_tagged).
name: conditional_patterndescription: A module testing pattern matching in conditional expressionsshould_fail: 0tags: 12.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv']incdirs: []top_module: rc: 3internal compiler error: Unexpected index
name: conditional_patterndescription: A module testing pattern matching in conditional expressionsshould_fail: 0tags: 12.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv:9: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: matches%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv:26: Unsupported: SystemVerilog 2005 reserved word not implemented: tagged%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv:26: syntax error, unexpected IDENTIFIER%Error: Exiting due to 4 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv
name: conditional_patterndescription: A module testing pattern matching in conditional expressionsshould_fail: 0tags: 12.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv:9: syntax error, unexpected TOK_ID, expecting '(' or '['
name: conditional_patterndescription: A module testing pattern matching in conditional expressionsshould_fail: 0tags: 12.6.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(') typedef union tagged {PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv::21 error in parsing: (syntax error, unexpected ';', expecting '(') u tmp;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.6.3--conditional_pattern.sv::26 error in parsing: (syntax error, unexpected vSYMBOL_ID) val = (tmp matches tagged a '{4'b01zx, .v}) ? 1 : 2;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 0
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 0
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 0
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv:9: syntax error, unexpected TOK_ID
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '=') for (int i = 0; i < 256; i++)ERROR (4)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 0
name: for_loopdescription: A module testing for loopshould_fail: 0tags: 12.7.1files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.1--for.sv']incdirs: []top_module: rc: 0module for_tb; initial begin begin : sv2v_autoblock_0 reg signed [31:0] i; for (i = 0; (i < 256); i = (i + 1)) $display("%d", i); end endendmodule
name: repeat_loopdescription: A module testing repeat loopshould_fail: 0tags: 12.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv:8: syntax error, unexpected '=', expecting '(' or '['
name: repeat_loopdescription: A module testing repeat loopshould_fail: 0tags: 12.7.2files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv::8 error in parsing: (syntax error, unexpected '=', expecting '(') int a = 128;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv::10 Unsuported token repeat(a) ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.2--repeat.sv::10 error in parsing: (syntax error, unexpected '(') repeat(a)ERROR (6)::PARSE_ERROR Parser found (1) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: foreach_loopdescription: A module testing foreach loopshould_fail: 0tags: 12.7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') string test [4] = '{"111", "222", "333", "444"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv::11 error in parsing: (syntax error, unexpected vCFUNC, expecting ';') $display(i, test[i]);ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: foreach_loopdescription: A module testing foreach loopshould_fail: 0tags: 12.7.3files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.3--foreach.sv:8: error: Cannot assign to array test. Did you forget a word index?Elaboration failed
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv:8:20: error: language feature not yet supported string test [4] = '{"111", "222", "333", "444"}; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 0
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 0
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv:8: syntax error, unexpected '=', expecting '('
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') string test [4] = '{"111", "222", "333", "444"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') int i = 0;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv:8: error: Cannot assign to array test. Did you forget a word index?Elaboration failed
name: while_loopdescription: A module testing while loopshould_fail: 0tags: 12.7.4files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.4--while.sv:8:9: Parse error: unexpected token 'string' (KW_string).
name: dowhile_loopdescription: A module testing do..while loopshould_fail: 0tags: 12.7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv']incdirs: []top_module: rc: 1../../home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv:8:20: error: language feature not yet supported string test [4] = '{"111", "222", "333", "444"}; ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
name: dowhile_loopdescription: A module testing do..while loopshould_fail: 0tags: 12.7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv::8 error in parsing: (syntax error, unexpected '[', expecting '(') string test [4] = '{"111", "222", "333", "444"};PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv::10 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting voLTE or '=') int i = 0;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: dowhile_loopdescription: A module testing do..while loopshould_fail: 0tags: 12.7.5files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.5--dowhile.sv:8: error: Cannot assign to array test. Did you forget a word index?Elaboration failed
name: forever_loopdescription: A module testing forever loopshould_fail: 0tags: 12.7.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv']incdirs: []top_module: rc: 10%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv:9: Unsupported: Verilog 1995 reserved word not implemented: fork%Warning-STMTDLY: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv:13: Unsupported: Ignoring delay on this delayed statement.%Warning-STMTDLY: Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message.%Error: /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv:14: Unsupported: Verilog 1995 reserved word not implemented: join%Error: Exiting due to 2 error(s)%Error: See the manual and http://www.veripool.org/verilator for more assistance.%Error: Command Failed /usr/bin/verilator_bin -Wno-fatal --cc /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv
name: forever_loopdescription: A module testing forever loopshould_fail: 0tags: 12.7.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv:10: syntax error, unexpected TOK_ID
name: forever_loopdescription: A module testing forever loopshould_fail: 0tags: 12.7.6files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::9 Unsuported token fork ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::10 Unsuported token forever begin : loop ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::12 error in parsing: (syntax error, unexpected ':') end : loopPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::13 Unsuported token #100 disable loop; ^~~~PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.7.6--forever.sv::14 Unsuported token join ^~~~ERROR (8)::PARSE_ERROR Parser found (4) errors in your syntax, exitingAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/odin_error.cpp]verify_delayed_error::30
name: jump_return_exprdescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: jump_returndescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv:8: syntax error, unexpected TOK_ID, expecting ';' or '('
name: jump_breakdescription: A module testing break statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv:9: syntax error, unexpected TOK_ID
name: jump_continuedescription: A module testing continue statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv']incdirs: []top_module: rc: 1-- Executing script file `scr.ys' --1. Executing Verilog-2005 frontend.ERROR: Parser error in line /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv:9: syntax error, unexpected TOK_ID
name: jump_return_exprdescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function int fun(input int a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv::9 error in parsing: (syntax error, unexpected '*', expecting '(') return a * 3;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: jump_returndescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv::8 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '(' or ';') function void fun(input int a);PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv::11 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') return;PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv::13 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') return;ERROR (6)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: jump_breakdescription: A module testing break statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '=') for (int i = 0; i < 256; i++)beginPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv::12 error in parsing: (syntax error, unexpected ';', expecting vSYMBOL_ID or '#') break;ERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: jump_continuedescription: A module testing continue statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv']incdirs: []top_module: rc: -6--------------Odin has decided you MAY fail ... :WARNING (1)::ARG_ERROR Permissive flag is ON. Undefined behaviour may occurWARNING (2)::ARG_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv::1 File (/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv) has an unsupported extension (.sv), Odin only supports { .v .vh }PARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv::9 error in parsing: (syntax error, unexpected vSYMBOL_ID, expecting '=') for (int i = 0; i < 256; i++)beginPARSE_ERROR /home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--continue.sv::13 error in parsing: (syntax error, unexpected vEND) endERROR (5)::NETLIST_ERROR Could not find a top level moduleAssertion failed()@[/home/travis/build/SymbiFlow/sv-tests/third_party/tools/odin_ii/ODIN_II/SRC/netlist_create_from_ast.cpp]find_top_module::295
name: jump_returndescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv']incdirs: []top_module: rc: 134/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv:11: error: Return from jump_tb.fun requires a return value expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv:13: error: Return from jump_tb.fun requires a return value expression./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv:17: warning: User function 'fun' is being called as a task./home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return.sv:17: assert: elab_expr.cc:1264: failed assertion 0Aborted (core dumped)
name: jump_breakdescription: A module testing break statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv']incdirs: []top_module: rc: 1/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--break.sv:12: sorry: break statements not supported.
name: jump_return_exprdescription: A module testing return statementshould_fail: 0tags: 12.8files: ['/home/travis/build/SymbiFlow/sv-tests/tests/chapter-12/12.8--return_val.sv']incdirs: []top_module: rc: 0module jump_tb; function signed [31:0] fun; input reg signed [31:0] a; fun = (a * 3); endfunction initial begin begin : sv2v_autoblock_0 reg signed [31:0] i; for (i = 0; (i < 256); i = (i + 1)) begin $display(fun(i)); end end endendmodule